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iniewski
Exactly my thinking Pushkar, there is a big difference between technology ...
Pushkar Ranade
TMSC’s warning about cost/complexity of EUV at 14nm and delays in the 450mm ...
TSMC says equipment vendors late for 14 nm
Rick Merritt
9/7/2011 6:08 AM EDT
TAIPEI – Time is running out to make critical decisions for how to make 14-nm chips expected to hit production in 2015, and capital equipment vendors are falling behind. That was the upshot of a talk by the top R&D executive at Taiwan Semiconductor Manufacturing Co. (TSMC) at Semicon Taiwan here.
TSMC believes it needs to move to next-generation lithography and 450-mm wafers to make 14-nm chips cost effectively, but capital equipment makers threaten to miss the foundry's schedule on both fronts. "Every day we become more and more concerned," said Shang-Yi Chiang, senior vice president of R&D of TSMC.
Fabs need throughput of more than 100 wafers per hour. But so far extreme ultraviolet (EUV) lithography offers just five wafers per hour at best. Two alternatives using multiple e-beam direct write approaches get less than one.
Similarly, TSMC "put out our wish list for 450-mm wafers a few months ago, but some in the capital equipment industry felt it was too aggressive so now we don’t know" what the schedule will be, Chiang said to EE Times after his talk. "We may have to do what we did at the 130-nm generation when some capacity was on 200- and some on 300-mm wafers," he said.
TSMC currently plans to bring up a pilot 450-mm wafer line at its Fab 12 in Hsinchu, followed by a production line in Taichung. The larger wafers are needed both to help keep pace with Moore's Law and to lower wafer costs as much as 30 percent.
The 450-nm wafers enable foundries to use fewer fabs, saving significant money on both land and labor costs. To meet expected demand for 32 million eight-inch equivalent wafers, TSMC could hire 20,000 engineers to run 22 plants. If it has to use today's 300-mm wafers the same output would require 29 plants and 27,000 engineers, Chiang estimated.
"450-mm wafers are not a technical issue but an economic issue which is probably more important than technical issue these days," Chiang said.
In lithography, today's 193-nm immersion systems will serve both the 28-nm node TSMC is ramping now and the next-generation 20-nm node. But at 20 nm, fabs will need to use double patterning, essentially running wafers through some exposure processes twice to draw finer lines.
At 14 nm the amount of double patterning with immersion systems could become prohibitively expensive for many customers. So TSMC will start testing a prototype 3100 series EUV machine from ASML in two weeks. It has already been testing an e-beam system from Mapper Lithography BV and will install another from KLA Tencor next year.
"If we cannot get EUV or e-beam to 100 wafers per hour throughput, we see few customers will be willing to continue migrating to finer technology nodes because of the cost," he warned.
TSMC hopes to ramp a 14-nm process in 2015 so "we have to make this decision [on lithography] early next year," Chiang said. "If we focus on using 193-nm immersion it becomes difficult to switch to EUV later on, [and] design rules will be defined based on the choice of lithography, so time is running out," he said.
450mm wafers cut engineering and land costs, TSMC said.
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resistion
9/7/2011 8:30 AM EDT
I think tsmc will be ok with DP if the volume per mask goes up a lot. This will happen if they gain market share against GF and Samsung. Otherwise, if market share loss is imminent, maskless would give them more agility.
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resistion
9/7/2011 9:57 AM EDT
I should say market share meaning more customers giving 100% business to tsmc.
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rfab
9/8/2011 12:04 AM EDT
1 think you"re tsmc"s pr
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resistion
9/8/2011 4:39 AM EDT
This article was about tsmc, so I used tsmc as subject. I think GF is also investigating maskless (same reasons).
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Or_Bach
9/7/2011 6:20 PM EDT
More volume is not always make it better, some times it just means that you are going to loose more. Cost of next generation device could be less attractive if you account the true cost of capital -throughput - and yield. As the issues with the classic 0.7x scaling are mounting up it seems that the industry should make serious effort to explore the monolith 3D IC alternative.
In fact I have no doubts that future progress needs to incorporate scale up if only to extend the useful life of the accelerating
costs associated with next generation lithography.
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resistion
9/7/2011 8:52 PM EDT
I agree the NGL is still not cost effective enough. But how does double patterning compare with stacking two wafers? It seems you still consume twice as much silicon area with stacking.
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Or_Bach
9/7/2011 11:41 PM EDT
Yes it appears so but it is not so. If we can stack two layers with rich vertical connectivity (monolithic 3D)you reduce by ~50% your average gate length which allow the average gate size (W/L) to be about 50% smaller which result in 50% reduction of active silicon area (Yes those repeaters and drive do consume area). Please feel free to use the IntSim v2.0 an open-source simulator available at http://www.monolithic3d.com/simulators.html to evaluate alternatives of device implementations and the implication on die size power and performance. And you get additional saving on equipment amortization cost, mature line yield and far lower masks cost.
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resistion
9/8/2011 4:32 AM EDT
Ok, just asking, not judging. Counting process steps is a serious exercise.
I will take a look at your simulators, thanks.
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resistion
9/8/2011 4:52 AM EDT
So I have 2 GB DRAM by stacking 1GB on another one. But I still patterned a 1GB die twice.
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RobDinsmore
9/8/2011 12:20 PM EDT
I don't understand why foundries/ logic companies keep talking about 450mm for 2015. I mean yeah, I get it, but it is pure fantasy at this point because nobody in the capital equipment industry has jumped in to support this yet and it will take a few years to get to the point where fabs can start developing their full flows and then the usual 2 until that flow is ready to ramp. I work in the industry and every time a colleague asks management about 450mm we get the same story they are telling the press. Namely that 450mm needs investment from customers or some yet to be decided collaboration to make it cost effective for equipment vendors.
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docdivakar
9/8/2011 1:57 PM EDT
@RobDinsmore: agree with some points you make above. The industry is still struggling with handling thinned wafers (like 3um, as in what is needed for 3D chip stacking) at 300mm. Handling thin wafers at 450mm will be exponentially harder. Secondly, there aren't many companies left in the test space to provide wafer probing gear (probe cards, test interfaces, etc) so the cost of NRE will be quite high. I think 450mm for 2015 is too optimistic unless the market needs change drastically by then.
Dr. MP Divakar
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docdivakar
9/8/2011 1:59 PM EDT
OOPS, I meant 30um above, not 3um!
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iniewski
9/8/2011 2:14 PM EDT
There is no way we will see 14nm chips in 2015. I am willing to make financial bets;-). Pls email kris.iniewski@gmail.com
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any1
9/8/2011 4:05 PM EDT
I believe that we could indeed see 14 nm design node chips in 2015. I believe that Intel and others see a clear path for multiple patterning using optical lithography at 14 nm. But because this approach is so expensive chip companies are looking for cost reductions elsewhere - such as the economy of scale of switching to 450 mm wafers to help offset the increased expense of lithography. The bigger question is will those companies be able to make any money on those chips?
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any1
9/8/2011 4:15 PM EDT
I would speculate that optical lithography with multiple patterning and all the other process tricks and advanced layout schemes could get us down to about 11 nm. If EUVL is not more capable and cost effective by then we will see the effective end of Moore's law.
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chipmonk
9/9/2011 2:52 PM EDT
The message here is that TSMC does not have what it takes to go to 14 nm on its own. Its waiting for Intel to figure it all out and then once again will get the technology free via the equipment suppliers ( as happened with ALD for gate last HKMG ) - albeit 2 years later. What if Intel now decides to do a lot more of the tool development for future nodes in - house and thus crush these bottom - feeding pretenders ?
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resistion
9/11/2011 10:54 AM EDT
No company can go purely on its own anymore.
At least lithographically, Intel's risk is reduced by memory makers esp. NAND flash like Micron and Toshiba. They validate existing lithography tools can go down to 1X nm. Logic half-pitch is actually a generation behind NAND flash.
As for high-k, some may question if it really is advantageous. Qualcomm for example, skipped on high-k at 28 nm. And Atom power consumption is still considered pretty high. So if tsmc bet all on high-k like Intel, that would have been an instance where it would have been wrong.
The newest development is the finfet or multigate, which Intel showed at 22 nm. But this technology was already available years ago.
Intel should get credit for reducing the risk of transitions like these. But these transitions for Intel are for only one type of product, x86 microprocessors, which hardly applies to memory makers or fabless/foundries.
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rfab
9/11/2011 9:55 PM EDT
Atom power and design more relevant, because the X86 complicated than ARM
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Pushkar Ranade
9/13/2011 5:05 PM EDT
TMSC’s warning about cost/complexity of EUV at 14nm and delays in the 450mm transition supports a growing pool of evidence that the 28/20nm nodes will be in production much longer than historical life cycle. This suggests that device-level innovation will need to continue on the planar transistor platform into the foreseeable future. Foundries and design houses alike will seek to enhance power/performance trade-off and try to maximize product level benefit from 28nm/20nm technologies. A 14nm technology is certainly physically achievable, but its likely going to be limited by cost/economics.
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iniewski
9/13/2011 5:10 PM EDT
Exactly my thinking Pushkar, there is a big difference between technology feasability and economical volume production, a distinction that some commentators above seem to neglect...Kris
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