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iniewski
Exactly my thinking Pushkar, there is a big difference between technology ...
Pushkar Ranade
TMSC’s warning about cost/complexity of EUV at 14nm and delays in the 450mm ...
TSMC says equipment vendors late for 14 nm
Rick Merritt
9/7/2011 6:08 AM EDT
Chiang suggested immersion lithography would be too expensive at 14 nm, exceeding traditional guidelines of half the capital equipment costs for a node. Despite the enormous costs of EUV and e-beam machines, estimated at as much as $120 million, they are still cheaper than immersion given the double patterning problems.
E-beam and EUV systems cost roughly the same. But E-beam systems currently under test do not require masks so could slightly cheaper to use than EUV, Chiang said.
EUV has "the broadest support and is the most likely route" forward, said Luc Van den hove, chief executive of the Imec research consortium based outside Brussels. "But this year and next we have to demo the production worthiness of this technology," Van den hove said in a separate talk.
Imec has been running wafers through an ASML 3100 pre-production system for three months "and we've seen improvement in throughput, but progress has been too slow and we have to further accelerate it," he said.
The power of the EUV source light is still too low, despite defining two approaches to creating the light source. "Progress has not been sufficient, and this is one of the highest priorities," said Van den hove who once ran Imec's lithography program.
As if the capital equipment problems were not enough, TSMC expects it will need to transition to a new transistor design at 14 nm, likely a FinFET. Intel announced plans to use such a 3-D transistor design starting at 20 nm.
Both TSMC and GlobalFoundries believe planar transistors can be used down to 20 nm. But they both expect to make the switch to 3-D structures such as FinFETs or fully depleted SOI at 14 nm.
Van den hove said FinFETs "are probably the most likely way. Beyond that we believe another technology breakthrough will be needed likely using super-high mobility materials such as germanium p-channel and III-IV materials for n-channels for 10 nm nodes," he added.
The good news is unexpected innovations have powered the industry past roadblocks in previous generations, despite as many as ten past predictions that Moore's law would end, said Chiang of TSMC. Based on feasibility demonstrations, he projected currently defined technologies could take CMOS scaling to geometries as fine as 7 nm.
E-beam lithography could have the lowest costs, TSMC said.
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resistion
9/7/2011 8:30 AM EDT
I think tsmc will be ok with DP if the volume per mask goes up a lot. This will happen if they gain market share against GF and Samsung. Otherwise, if market share loss is imminent, maskless would give them more agility.
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resistion
9/7/2011 9:57 AM EDT
I should say market share meaning more customers giving 100% business to tsmc.
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rfab
9/8/2011 12:04 AM EDT
1 think you"re tsmc"s pr
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resistion
9/8/2011 4:39 AM EDT
This article was about tsmc, so I used tsmc as subject. I think GF is also investigating maskless (same reasons).
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Or_Bach
9/7/2011 6:20 PM EDT
More volume is not always make it better, some times it just means that you are going to loose more. Cost of next generation device could be less attractive if you account the true cost of capital -throughput - and yield. As the issues with the classic 0.7x scaling are mounting up it seems that the industry should make serious effort to explore the monolith 3D IC alternative.
In fact I have no doubts that future progress needs to incorporate scale up if only to extend the useful life of the accelerating
costs associated with next generation lithography.
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resistion
9/7/2011 8:52 PM EDT
I agree the NGL is still not cost effective enough. But how does double patterning compare with stacking two wafers? It seems you still consume twice as much silicon area with stacking.
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Or_Bach
9/7/2011 11:41 PM EDT
Yes it appears so but it is not so. If we can stack two layers with rich vertical connectivity (monolithic 3D)you reduce by ~50% your average gate length which allow the average gate size (W/L) to be about 50% smaller which result in 50% reduction of active silicon area (Yes those repeaters and drive do consume area). Please feel free to use the IntSim v2.0 an open-source simulator available at http://www.monolithic3d.com/simulators.html to evaluate alternatives of device implementations and the implication on die size power and performance. And you get additional saving on equipment amortization cost, mature line yield and far lower masks cost.
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resistion
9/8/2011 4:32 AM EDT
Ok, just asking, not judging. Counting process steps is a serious exercise.
I will take a look at your simulators, thanks.
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resistion
9/8/2011 4:52 AM EDT
So I have 2 GB DRAM by stacking 1GB on another one. But I still patterned a 1GB die twice.
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RobDinsmore
9/8/2011 12:20 PM EDT
I don't understand why foundries/ logic companies keep talking about 450mm for 2015. I mean yeah, I get it, but it is pure fantasy at this point because nobody in the capital equipment industry has jumped in to support this yet and it will take a few years to get to the point where fabs can start developing their full flows and then the usual 2 until that flow is ready to ramp. I work in the industry and every time a colleague asks management about 450mm we get the same story they are telling the press. Namely that 450mm needs investment from customers or some yet to be decided collaboration to make it cost effective for equipment vendors.
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docdivakar
9/8/2011 1:57 PM EDT
@RobDinsmore: agree with some points you make above. The industry is still struggling with handling thinned wafers (like 3um, as in what is needed for 3D chip stacking) at 300mm. Handling thin wafers at 450mm will be exponentially harder. Secondly, there aren't many companies left in the test space to provide wafer probing gear (probe cards, test interfaces, etc) so the cost of NRE will be quite high. I think 450mm for 2015 is too optimistic unless the market needs change drastically by then.
Dr. MP Divakar
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docdivakar
9/8/2011 1:59 PM EDT
OOPS, I meant 30um above, not 3um!
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iniewski
9/8/2011 2:14 PM EDT
There is no way we will see 14nm chips in 2015. I am willing to make financial bets;-). Pls email kris.iniewski@gmail.com
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any1
9/8/2011 4:05 PM EDT
I believe that we could indeed see 14 nm design node chips in 2015. I believe that Intel and others see a clear path for multiple patterning using optical lithography at 14 nm. But because this approach is so expensive chip companies are looking for cost reductions elsewhere - such as the economy of scale of switching to 450 mm wafers to help offset the increased expense of lithography. The bigger question is will those companies be able to make any money on those chips?
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any1
9/8/2011 4:15 PM EDT
I would speculate that optical lithography with multiple patterning and all the other process tricks and advanced layout schemes could get us down to about 11 nm. If EUVL is not more capable and cost effective by then we will see the effective end of Moore's law.
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chipmonk
9/9/2011 2:52 PM EDT
The message here is that TSMC does not have what it takes to go to 14 nm on its own. Its waiting for Intel to figure it all out and then once again will get the technology free via the equipment suppliers ( as happened with ALD for gate last HKMG ) - albeit 2 years later. What if Intel now decides to do a lot more of the tool development for future nodes in - house and thus crush these bottom - feeding pretenders ?
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resistion
9/11/2011 10:54 AM EDT
No company can go purely on its own anymore.
At least lithographically, Intel's risk is reduced by memory makers esp. NAND flash like Micron and Toshiba. They validate existing lithography tools can go down to 1X nm. Logic half-pitch is actually a generation behind NAND flash.
As for high-k, some may question if it really is advantageous. Qualcomm for example, skipped on high-k at 28 nm. And Atom power consumption is still considered pretty high. So if tsmc bet all on high-k like Intel, that would have been an instance where it would have been wrong.
The newest development is the finfet or multigate, which Intel showed at 22 nm. But this technology was already available years ago.
Intel should get credit for reducing the risk of transitions like these. But these transitions for Intel are for only one type of product, x86 microprocessors, which hardly applies to memory makers or fabless/foundries.
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rfab
9/11/2011 9:55 PM EDT
Atom power and design more relevant, because the X86 complicated than ARM
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Pushkar Ranade
9/13/2011 5:05 PM EDT
TMSC’s warning about cost/complexity of EUV at 14nm and delays in the 450mm transition supports a growing pool of evidence that the 28/20nm nodes will be in production much longer than historical life cycle. This suggests that device-level innovation will need to continue on the planar transistor platform into the foreseeable future. Foundries and design houses alike will seek to enhance power/performance trade-off and try to maximize product level benefit from 28nm/20nm technologies. A 14nm technology is certainly physically achievable, but its likely going to be limited by cost/economics.
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iniewski
9/13/2011 5:10 PM EDT
Exactly my thinking Pushkar, there is a big difference between technology feasability and economical volume production, a distinction that some commentators above seem to neglect...Kris
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