Preview: Conference looks beyond 32-nm to 3-D

The 2011 Advanced Metallization Conference (AMC), Oct. 4-6 in San Diego will be the 28^th conference in a series devoted to leading-edge research in the field of advanced metallization and 3-D integration for ULSI IC applications.  This year’s program emphasizes the challenges with taking Cu/ULK beyond 32 nm and characterizing 3-D TSV technology, but also has strong sessions on metal gate/high K, materials for memory, and emerging technologies.  It will be followed Oct. 6 by a Sematech-organized 3D workshop on Process Technology Challenges for 3-D Interconnects at the same venue.

AMC is a single-session conference with time for networking and technical discussion. The conference provides a forum for open discussion of important issues affecting state-of-the-art and future directions in interconnect systems. The strength of the AMC 2011 lies in two areas: Cu/ULK interconnect issues and 3-D integration. 

The conference features one day on Cu Barriers, ultra-low-K dielectric (ULK) materials and integration and Interconnect Reliability.  During this day, IBM will reveal the addition of Mn to their 32-nm Cu technology, and IBM, Tokyo Electron, and two universities will review the challenges and advantages of utilizing Ru as a new barrier for Cu interconnects.  STMicroelectronics will introduce integrated dielectric capping for Reliability enhancement at the 28-nm Technology Node, and Infineon will add more functionality to technologies and products that use Cu metallization. In the same session, Globalfoundries will present research on designing porous ULK dielectrics with varying porosity, pore structure, and carbon bonding to meet scaling challenges to sub-80-nm pitch copper lines. Electromigration, stress-migration, stress-induced voiding and dielectric breakdown in advanced interconnect technologies are active topics for the interconnect reliability session, which includes talks from IBM, IMEC, Novellus, University of Texas and RPI. 

The first technical session on Memory Devices includes an invited talk on RRAM Materials in Integration by IMEC, which follows the keynote talk by Robert Patti, CEO of Tezzaron Semiconductor Corp., on Ultra High-Density 3-D Memory Products. Bob will show that standard processing techniques can be used to separately fabricate memory, logic, and analog functions that are then assembled into a single, tightly integrated 3-D circuit. This true 3-D circuit assembly can bring gigabytes of memory to within tens of microns – and mere picoseconds – of the data processing elements, without any process compromises. 

The final day of the conference will tackle 3-D Integration, 3-D characterization and Packaging challenges for the Integrated Circuit Industry.  The performance limitations of Cu/ULK that lead to the insertion of alternatives will be reviewed in a talk by Professor Krishna Saraswat.  Novel analytical techniques for characterizing 3-D integrations will be the focus of this intense session, with novel TSV characterization methods being shown by four institutions (Stanford University, Fraunhofer IZPF, Globalfoundries, and Nagoya University).   

With 3-D integrated circuits, the through silicon via (TSV) is a critical element connecting die-to-die in the integrated stack structure. The high aspect ratio and the thermal mismatch between TSV and Si can induce complex and sufficient stresses to drive interfacial crack growth and Cu protrusion in 3-D interconnects, degrading the performance of stress-sensitive components in digital and analog circuits. The effect of process-induced stresses on the thermo-mechanical reliability of TSV structures will be reviewed by the University of Texas.

The introduction of high-k dielectrics and metal gates is a paradigm shift in materials for the semiconductor industry. High-k dielectrics and metal gates (HKMG) can reduce the gate leakage in transistor devices over several orders of magnitude while simultaneously reducing the equivalent oxide thickness. This combination of new materials delivers faster transistor switching at lower leakage values and in turn enables continued device scaling for future technology nodes and has been billed the one of the top 10 Fab challenges by EE Times. In a robust Metal Gate and High K Session, IBM will present the latest materials and integration challenges with High K and Metal Gate transistors, while STMicroelectronics, UMC and Applied Materials will highlight the process integration issues with the technology.

The Emerging Technologies Session of the conference features talks on Carbon Nanotubes (LEAP), Graphene (University of Tokyo), and RF MEMS (Tokyo Institute of Technology), as well as a talk on Magnetic Inductors from Intel.  Paul Fischer from Intel will highlight their work using on chip, thin film magnetic inductors to enable miniaturization and improve power management with decreased voltage droop and increased regulator response time due to proximity.

AMC typically highlights both fundamental and applied research as well as manufacturing and implementation challenges. The 2011 program is no exception to that rule, but AMC 2011 also includes contributions on unit process development, fully integrated technology, and interconnect reliability.  Come for the Cu scaling and 3-D integration papers, but stay for the contributions on gate stack and memory materials and the Sematech Workshop that follows on Oct. 6. The program is strong this year.

Visit the conference website for the latest conference information.  Advanced registration and the discounted registration fee ends on September 15, 2011. See you there!

--Paul Besser is a fellow in Globalfoundries' Advanced Module Technology Development Group