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KB3001

9/24/2011 1:18 PM EDT

I find the idea quite middle of the road :-)

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resistion

9/23/2011 8:44 AM EDT

It's a large and doubly processed die. So such cost can be tolerated? Great!

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Update: Nvidia five-core chip ups mobile ante

Rick Merritt

9/21/2011 2:12 AM EDT

SAN JOSE, Calif. – Nvidia will pack five cores into its next-generation mobile CPUs using a novel technique it describes as Variable Symmetric Multiprocessing (vSMP) to claim a power efficiency edge over rivals Qualcomm and Texas Instruments.

The company revealed in a blog posting Tuesday (Sept. 20) its quad-core Kal-El processor first shown in February actually has a fifth core. The extra core takes over automatically when workloads permit running the system in a low power mode.

Nvidia described the vSMP approach in a white paper describing the chip, also known as Tegra 3. The device uses what Nvidia calls a CPU Goveror and CPU management logic to analyze system workloads and automatically switch between the one low power core, called a Companion core, or the quad-core complex as needed for maximum efficiency.

Both cores are based on the ARM Cortex A9. The Companion core running up to 500 MHz is made in a low power process technology; the quad core complex running up to a GHz is made in a general purpose or high performance process.

Despite the difference in process technology, the low power and high performance cores share the same die. When using the quad-core complex, the Companion core is shut down and the device activates one to four of its main cores depending on the performance needs of the workload.

The chip can switch between the Companion and main cores in less than 2 milliseconds.  "The Companion and main cores share the same L2 cache, and the cache is programmed to return data in the same number of nanoseconds for both Companion and main cores," the white paper said.

Nvidia claims the approach provides power savings in all use modes ranging from 14 to 61 percent compared to a standard quad core. In a rare direct comparison with competing chips, Nvidia said the five-core chip consumes two to three times less power than chips from Qualcomm and Texas Instruments.

The Nvidia chip consumes 579 milliwatts when performing at about 5,000 Coremarks and running at 480 MHz. By contrast the TI Omap 4 and Qualcomm Snapdragon QC8660 consume 1501 and 1453 mW respectively at roughly the same performance level attained when running at about 1 GHz, Nvidia claimed.

In addition, when running at 1 GHz the Nvidia chip performed 11,667 on the Coremark benchmark and still consumed less power than the competing chips at 1261 mW, it said.

"This could be just elegant technology that doesn't make a significant difference for users, or it could help differentiate Nvidia--we will have to wait to see when systems ship," said Nathan Brookwood, principal of market watcher Insight64 (Saratoga, Calif.).

The wait won't be long. The Nvidia chip is expected to appear in systems in time for the 2011 holiday shopping season. Competing quad-core chips will likely appear this year, too,  but probably not without this novel innovation.

Qualcomm announced plans for a quad-core Snapdragon in February, but has not released details of the chip. TI has described its plans for its Omap 5 using dual ARM Cortex A15 cores.

Analysts believe the quad core processors will initially be confined to use in tablets because of the heat they generate.

"Some of the initial quad-core designs will exceed the thermal limits of what you can do in a smartphone, so you will need to throttle them back and then you won't get the performance you expect," said Linley Gwennap, principal of the Linley Group in a talk earlier this year. "Thus quad-cores will be more successful in tablets initially because of their better heat dissipation" until 28nm versions for smartphones are available, he said.

However, Nvidia has promised that its Tegra 3 will fit into the same power profile as the existing dual-core Tegra 2. Even if it does make the power budget for smartphones, the chip is unlikely to appear in handsets this year given the relatively long cellphone qualification cycles with regulators and carriers.

In a separate paper, Nvidia talked about the advantages of quad core mobile chips. The company noted the Linux base of Android is well attuned to multicore and multithreaded software support in Webkit and Firefox browsers.

Nvidia's crude rendering of its five-core Kal-El.





Neo1

9/21/2011 5:44 AM EDT

Impressive and I guess this takes the smartphones and Tablets to a level close enough to dictate a fusion of high quality entertainment and communication devices.
With improved battery technology this could usher in a whole new way for web services and media content to present themselves on our so called phones.

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Robotics Developer

9/21/2011 10:57 AM EDT

Interesting idea, I wonder if others will pick up on this as a way to encourage longer battery life and more "instant on" performance?

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KB3001

9/24/2011 1:18 PM EDT

I find the idea quite middle of the road :-)

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jeremybirch

9/21/2011 11:15 AM EDT

You would not need to use two die for this, you can just synthesise against a low power rather than a high performance library. If leakage was the issue then you could use well bias tricks to get around it, or have a double oxide process to have thick oxides for the slow gates - this is a bit but not that rare, but two dies is surely a bad solution?

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Paul A. Clayton

9/21/2011 11:36 AM EDT

The white paper indicates that the shared L2 cache latency is the same for the 'Companion' core as for the other cores, so it is very unlikely that it is on a separate chip.

Furthermore, even with package-level integration, an additional chip hop (to reach L2 cache, memory controllers, and I/O interfaces) would presumably have a noticeable power penalty.

The table entries for Process Technology "Low Power (LP)" (for the Companion core) and "General/Fast (G)" does imply different process, but this might be a simplification for the sake of the whitepaper's target audience.

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Paul A. Clayton

9/21/2011 11:42 AM EDT

I also just noticed the statement: "including the time to switch cores within the chip". While 'chip' is sometimes used loosely to refer to an integrated package, it seems likely in this case that it is a single die.

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Frank Eory

9/21/2011 4:17 PM EDT

Agreed. Rick, you did not need to go out on a limb with "Although it provided no details, Nvidia presumably implements the device as two die in a system-in-package."

The companion core could easily have been synthesized with the LP (high Vt) library, and the rest of the chip synthesized with the GP (lower Vt) library and integrated on a single die.

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kmonsen

9/21/2011 4:44 PM EDT

Besides high Vt vs. low(er) Vt, There are other variations of libraries, as well:
- 9-track vs. 12-track
- long-channel vs. short-channel
(The latter makes a big difference in the leakage characteristic, especially how much it goes up at high temperature.)

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stixoffire

9/23/2011 3:11 AM EDT

According to the article they are all on the same die.

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stixoffire

9/23/2011 3:13 AM EDT

I should have put the quote. "Despite the difference in process technology, the low power and high performance cores share the same die. "

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AP81

9/21/2011 2:46 PM EDT

I wonder If software (OS) can cope up with these many cores. From hardware point of view, you can have as many cores as you want, whether software can take advantage of these cores ?

So far, I haven't seen multiple improvements in processing speed by increasing number of cores... comments will be appreciated.

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selinz

9/21/2011 4:25 PM EDT

There are typically so many unrelated things going on in a typical smartphone that I would think that multiple cores would be easily utilized.

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Athlor

9/21/2011 5:52 PM EDT

It sounds amazing, once again I'm surprised by Nvidia and I'm intrigued by the ways one could utilize this 5th companion core.

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ArtB_#1

9/21/2011 5:59 PM EDT

One unanswered question is whether a quad core plus a companion core for reducing power consumption will work better or more efficiently than the asynchronous cores developed by Qualcomm.

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chipchap42

9/21/2011 6:28 PM EDT

My impression having read their white paper is that this is probably what is known as a "2.5D chip". You cannot get enough power difference with libraries on leakage power so it looks like the low-power core is done using a 40LP process and the others with a 40G. A passive silicon interposer (like the one announced by Xilinx in its high-end V7 parts) would then connect the die, which would also allow the L2$ to communicate effectively. Well that's my guess anyway.

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resistion

9/22/2011 2:50 AM EDT

Sounds good to me. Will it be more likely Nvidia will later complain about yield again?

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agk

9/22/2011 7:39 AM EDT

A novel and innovative approach.Many times the processor needs to run simple applications like in a cell phone searching the names,storing the names,call records viewing,missed calls, setting up the musics and a big list of selections. While doing all these the companion core is more than sufficient. This will save battery power and plus less electromagnetic radiation to the user.

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rick.merritt

9/22/2011 1:53 PM EDT

Thanks all--and Nathan Brookwood especially--for helping me see this is a single die. Question: Is there anything novel here in how the chip understandes and responds to the system workload?

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Joe Byrne

9/22/2011 3:46 PM EDT

cf Marvell Armada 628 http://bit.ly/r1kEd4

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rick.merritt

9/22/2011 4:13 PM EDT

Thanks for weighing in Joe. A three-core Armada organized aloing similar lines as the Tegra 3, eh? So will this be a new trend? Do you think Marvell and Nvidia independently had the same idea?

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resistion

9/23/2011 8:44 AM EDT

It's a large and doubly processed die. So such cost can be tolerated? Great!

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