News & Analysis
Comment
iniewski
Very true Jim...and this situation is not going to change with silicon getting ...
Jim Finch
The primary reason startup companies spent so much money is because their ...
Debunking the myth of the $100M ASIC
Andreas Olofsson
10/3/2011 1:08 PM EDT
A false belief that leading-edge chips cost up to $100 million to develop has severely decimated levels of venture capital investment in semiconductors, diminishing innovation in our industry and our economy. The fact is, engineers can create a profitable chip company with less than $2 million of total investment. I know because we have done it.
An exponential increase in mask costs is cited most often as the reason chips have become so expensive. Mask costs have risen from $100,000 to as much as $1-$3 million, but this factor alone cannot explain why some chips costs $100 million to develop.
Some blame the high costs of EDA tools. While they are certainly not cheap, on a per-project basis EDA tool costs have actually decreased significantly. Today many leading-chips can be taped out using vanilla flows derived from reference scripts provided by the EDA vendor. Thus, per transistor and certainly per project, the cost of EDA tools has actually gone down in the last ten years.
Others say deep submicron design is getting really hard. This work definitely is not for hobbyists, but for a small expert team equipped with state-of-the-art tools, it is today possible to accomplish in weeks what used to take a generously sized team 6-9 months.
The most valid reason for the recent explosion in development costs is that chips are getting really complex. Indeed, design complexity is by far the biggest component in a SoC project’s costs, and it varies widely depending on the type of chip. A complex SoC can be a hundred times more complicated than a high performance ASIC. And, as experienced project managers know, complexity is always expensive whether it involves SoCs, FPGAs or software products.
Based on my personal experience, observations and conversations with chip startup executives who spent, on average, $50 million on SoC development, engineering salaries are by far the biggest cost in SOC design. (See figure below.)
Typical development costs for a complex SoC product (Total: ~$50M)
What market you choose is the most important decision determining the cost of chip development. Markets that are not quite as cost- and space-sensitive as consumer devices have a huge advantage in development cost savings, because they allow companies to leverage existing technology to make chip set solutions that satisfy the system requirements. At Adapteva, we chose military, embedded computing and high performance computing as initial markets because of readiness of the market and the capability to customize for these markets.
Here are a few other simple ways to reduce chip product development expenses:
- Reduce the feature set that needs to be implemented.
- Maximize the reuse of validated blocks and RTL code.
- Leverage off-the-shelf technology.
- Recycle all the great chip ideas of the last 70 years
- Design architectures that leverage existing open-source software.
- Make processors programmable in C.
- Make the chip attractive and easy enough to use, so that the user won’t mind programming it himself.
Designing architectures that can easily be verified with a small team is an art form that requires very tight integration between the architecture, design and verification teams. At Adapteva, we staffed-up extremely slowly and took our time to perfect the mask cost until absolutely ready. The unity of the design team was critical to our success.
Focusing on the company’s core competency is critical in order to keep costs under control. We were lucky to find great tier-one development partners for manufacturing, development tools, board development and marketing.
At Adapteva, we used many of these techniques to reduce each cost item by more than 90 percent. We have now reached product release and a company break–even point with less than $2 million of total investment. Along the way, we completed four generations of our Epiphany multicore products.--Andreas Olofsson is chief executive of Adapteva (Lexington, Mass.).
|
|
|
|
|
Marketing Guru
10/3/2011 4:45 PM EDT
Andreas,
In the real world, very few ASICs require the leading-edge technology that cost up to $100 million to develop. Such applications are limited in their deployment to multi-multi mega-million unit markets.
At JVD Inc., we focus on the Analog ASIC market, which, according to research firm IC Insights, constitutes almost 60% of the nearly $37B of Analog ICs sold in 2010. None of these come close to your cost projections…. Typical NRE + Tooling ranges from $250K to $650K, making them affordable to thousands of potential customers.
Bob Frostholm
Sign in to Reply
iniewski
10/3/2011 6:46 PM EDT
Good article Andreas, yes, $100M number refers to complex SOC types designed by Intel's, Nokia's and TI's of the world...I know first hand few small, analog ASICs that were developed under $2M, similalrly to the figures you are quoting...but the perception in VC community remains that IC design is very expensive...Kris
Sign in to Reply
Neo1
10/3/2011 11:23 PM EDT
It still is expensive not because it costs $100M but because it requires a team with a large set of skills and they don't come cheap. Even with a budget of tens of millions chips have been made but any further growth and advanced features will sink in more money than you started out with and evetuallu it becomes a successful self sustaining product but by that time your expenses have neary shot up to 2 to 4 times your start up budget.
Sign in to Reply
Mike.Beunder
10/4/2011 4:32 AM EDT
As the graph shows, software has become the dominant cost factor for your hardware - just making the silicon doesn't give you a product, you need the software as well. If you can live of open source, that'll be great but most of the time you'll need to go through significant efforts to create the software required to make the chip into a product. And from there the acceptance of your product is set by the ability of your (potential) customers to get their apps running on your system. In short, putting out the (silicon) hardware is only (less than) half the job.
Sign in to Reply
iniewski
10/4/2011 10:32 AM EDT
This might be true for large SOC...but you don't have to write any software for a small analog or mixed-signal ASIC...Kris
Sign in to Reply
boblespam
10/4/2011 8:11 AM EDT
It's the cost of the employee turn over that is pointed out there. As said: slow recruitment and tightly united design team will make your company save time and a lot of money.
Sign in to Reply
KB3001
10/4/2011 8:23 AM EDT
It's about the risk (or perception of risk) rather than the actual cash investment needed. Many things could go wrong in the SoC business and Capital is a Coward...
Sign in to Reply
jeffw_00
10/4/2011 11:13 AM EDT
Well said Andreas. A small number of skilled, experienced people can wear many hats, strategically pick only the tools they really need, and get better, more cost-effective results than younger, cheaper, "armies".
Sign in to Reply
Robotics Developer
10/4/2011 5:11 PM EDT
Having worked in the ASIC industry for 18+ years I have seen the costs skyrocket from 30K to 1.5million. The real cost was not the NRE but the engineering cost to develop, test/simulate, PCB development and system level efforts. These get really expensive as the chip complexity goes up. That said, if you are doing plain vanilla design with low volumes most work shifted from ASICs to FPGAs. FPGAs were taking over the lower end designs both due to time to market and cost. The numbers of ASIC designers started to fade as fewer and fewer designs were attempted and companies shifted to FPGAs. Using an FPGA for the basic designs makes a lot of sense. The ease of reprogramming and quick turn times offsets the increased chip cost (per part) by allowing faster time to market. The last few chips I worked on were between 1.25 to 2.5 million for NRE alone and took over a year with 8 to 12 engineers. These were the only chips that made sense to engineer due to volume and performance drivers.
Sign in to Reply
Wilton.Helm
10/7/2011 2:57 PM EDT
No question FPGAs have had a huge impact, and by implication what's left for ASIC/SoC is going to be the higher end more costly designs which is a factor skewing the numbers.
But FPGAs are so cost effective and even power effecient that just about all but cutting edge, products or consumer products made in very large volumes simply cannot justify custom silicon compared to an FPGA solution.
For applications like the segment I'm in, they are absolute salvation. I've discussed with others before the trend towards ASIC and high integration and how small companies and niche markets that never sell things in million piece quantities can survive. The answer is simple. FPGA. The tools can be very affordable and the chips offer a huge amount of capability for very reasonable costs. There are even some out there with analog stuff in them, not to mention some pretty credible both hard and soft core CPU implementations.
Sign in to Reply
iniewski
10/4/2011 6:53 PM EDT
The trend of replacing ASICs with FPGA started several years back and will continue with accelerated force. I remember standing at one of the large telecom trade shows showing with pride our ASIC with a Xilinx guy standing behind me and smiling. My demo board had one ASIC surrounded by 8 FPGAs! Kris
Sign in to Reply
moloned
10/10/2011 12:27 PM EDT
I can see how you can get to a few 100s of MPW parts in 65nm, but I can't see how this gets you to several hundred $ each for your chips.
Care to explain?
In the case your customers are paying this kind of price the second question would be how you plan to scale from a niche product to the mass-market?
Sign in to Reply
iniewski
10/10/2011 12:32 PM EDT
To@moloned
If silicon die is about 1cm2 which is fairly typical you would hundreds of part in 0.35um 6 inch wafer...in 65nm the wafer size would be much larger, 8 or 12 inches so you will get way more than few hundreds...
I will leave to Andreas to explain your scaling question...Kris
Sign in to Reply
WaywardGeek
3/20/2012 4:08 AM EDT
Kudos, Andreas, on a very cool engineering feat. There are niche markets where MPW runs can be a viable production solution, like military, rad-hard, and space. Not every company has to be the next Intel to be successful. However, the reality is that Moore's Law is failing, bit by bit. Fewer and fewer designs make it into the latest fab processes, and the companies that do production there are huge corporations. Rarely do we see the innovative startups that drove Silicon Valley's success, at least in the IC space.
I am personally focusing on the mixed signal space, where competitive analog is still reasonably affordable. Even so, at Triad Semi, we focus on reducing up-front NRE, providing quick turn, and lowering risk, as these are issues strangling the industry.
So, both you and I have moved into niches where we can innovate at small companies without insane levels of venture funding. That's where Moore's Law is failing us the most. We may still be on track for 28nm and even the next node, but the tech explosion cannot be sustained without the Darwinian competition between new ventures. What are the latest super cool new ideas being produced in 28nm? Well, yours of course, but in volume we're seeing Apple add 4 ARM cores to their iPads. I guess the iPad 4 big innovation will be 8 cores? Then 16? And Intel... 8 cores in my next laptop, with a bigger on-chip GPU? Is this really innovation? Yes, transistors are getting cheaper, but they're also getting dumber, because we just can't afford to enable all the innovators to go be creative in 28nm. I pray for a breakthrough like low cost direct-write e-beam, or something that will enable advanced silicon within reach of a traditional startup.
Sign in to Reply
iniewski
3/20/2012 8:25 AM EDT
Keep praying @WaywardGeek...silicon industry has become very mature and real innovation is rare...it is quickly becoming another stable industry like car making for example...we have enjoyed the fun ride while it lasted for 50 years!...Kris
Sign in to Reply
Jim Finch
3/20/2012 2:21 PM EDT
The primary reason startup companies spent so much money is because their Generation 1 device is almost never commercially viable. It typically works just fine, even hits key performance specs, but the price performance advantage offered is not sufficient to convince potential customers to move away from their current suppliers. This forces additional time and money to develop Gen 2 and usually Gen 3 devices before the entity can generate significant revenue at acceptable margins. This process adds 3-5 years and $30-50M of wasted capital from a VC perspective. I believe this is the greatest spending culprit for most startup companies. Jim
Sign in to Reply
iniewski
3/20/2012 3:50 PM EDT
Very true Jim...and this situation is not going to change with silicon getting more complex...only people with deep pockets will be able to afford ASICs...Kris
Sign in to Reply