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MIPS, eSilicon tapeout 28-nm MPU cluster
10/5/2011 8:45 AM EDT
SAN FRANCISCO—Processor IP vendor MIPS Technologies Inc. and semiconductor value chain producer eSilicon Corp. Wednesday (Oct. 5) announced the tapeout of a high-performance, three-way microprocessor cluster on Globalfoundries Inc.'s low-power 28-nm process technology.
Wafers are currently running in Globalfoundries’ Fab 1 in Dresden, Germany, with silicon expected in early 2012, the companies said. SoC designs can start immediately, they said.
MIPS provided the RTL based on its MIPS32® 1074Kf Coherent Processing System (CPS), and eSilicon performed the synthesis and timing-driven layout, optimizing the design to achieve true worst-case performance of 1-GHz for the cluster, the companies said. Typical performance is expected to be approximately 1.5GHz, they said.
To reach the 1-GHz target without compromising low power, eSilicon’s custom memory team created custom fast cache instances for the L1 caches to replace standard memories that were in the critical path of the design, according to the company. The 1074Kf CPS is based on the combination of two high-performance technologies—coherent multiprocessing, and the superscalar, out-of-order MIPS32 74K processor core as the base CPU, according to eSilicon. The 74K core is a multi-issue, 15-stage out-of-order architecture already in production with numerous customers for digital televisions, set-top boxes and a variety of home networking applications and is broadly used in internet-connected digital home products, according to the company.
“This was an exciting project for our custom IP engineers," said Paul Hollingworth, vice president of strategic marketing at eSilicon, in a statement. "Our custom FCIs did the trick in enabling us to meet the fast-approaching shuttle date. Together with the high quality of the MIPS 1074K design, we were able to quickly meet the challenging performance targets in a low-power process."
Customers can license the 1-GHz implementation from eSilicon today—either as is or customized, according to the company. The cluster has been taped out as a test chip, and will be offered as a hard macro core, eSilicon said. It includes embedded design-for-test and design-for-manufacturing features and can be further customized and optimized to meet the specific needs of the application, the firm said. More information about the microprocessor cluster is available on eSilicon's website.
Wafers are currently running in Globalfoundries’ Fab 1 in Dresden, Germany, with silicon expected in early 2012, the companies said. SoC designs can start immediately, they said.
MIPS provided the RTL based on its MIPS32® 1074Kf Coherent Processing System (CPS), and eSilicon performed the synthesis and timing-driven layout, optimizing the design to achieve true worst-case performance of 1-GHz for the cluster, the companies said. Typical performance is expected to be approximately 1.5GHz, they said.
To reach the 1-GHz target without compromising low power, eSilicon’s custom memory team created custom fast cache instances for the L1 caches to replace standard memories that were in the critical path of the design, according to the company. The 1074Kf CPS is based on the combination of two high-performance technologies—coherent multiprocessing, and the superscalar, out-of-order MIPS32 74K processor core as the base CPU, according to eSilicon. The 74K core is a multi-issue, 15-stage out-of-order architecture already in production with numerous customers for digital televisions, set-top boxes and a variety of home networking applications and is broadly used in internet-connected digital home products, according to the company.
“This was an exciting project for our custom IP engineers," said Paul Hollingworth, vice president of strategic marketing at eSilicon, in a statement. "Our custom FCIs did the trick in enabling us to meet the fast-approaching shuttle date. Together with the high quality of the MIPS 1074K design, we were able to quickly meet the challenging performance targets in a low-power process."
Customers can license the 1-GHz implementation from eSilicon today—either as is or customized, according to the company. The cluster has been taped out as a test chip, and will be offered as a hard macro core, eSilicon said. It includes embedded design-for-test and design-for-manufacturing features and can be further customized and optimized to meet the specific needs of the application, the firm said. More information about the microprocessor cluster is available on eSilicon's website.
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