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docdivakar
Seems like a good start at 10um TSV. The article leaves out subsequent ...
resistion
No industry involvement means faster, more independent development but harder ...
R&D group begins TSV chip pilot production
10/11/2011 1:58 AM EDT
SAN FRANCISCO—All Silicon System Integration Dresden (ASSID), a microelectronic wafer-level packaging and system integration center backed by the government of the German state Saxony and operated by the Fraunhofer IZM Institute, has begun pilot-line production of 3-D semiconductor devices with through-silicon-vias (TSVs), according to a statement issued Monday (Oct. 10) by one of its suppliers, Altatech Semiconductor SA.
ASSID is developing enhanced 3-D integration, assembly and interconnection technologies to enable the heterogeneous integration of different chip functionalities within a single packaged device.
ASSID was established in 2009 by Saxony to stop the erosion of semiconductor manufacturing development around Dresden. At the time, the Saxon government claimed that ASSID would be the first research institute in the world dedicated to R&D on back-end 3-D chip production.
Altatech (Montbonnot, France) said ASSID is using a single-wafer, multi-chamber AltaCVD 300 system to deposit conformal dielectric liners inside TSVs to build 3-D system in package devices. The TSVs being filled have aspect ratios up to 10:1 and diameters as small as 10 microns, according to Altatech.
"We’re achieving excellent quality in film conformality, uniformity and integrity at low processing temperatures below 400°C," said M. Jürgen Wolf, manager of Fraunhofer IZM-ASSID, in a statement.
Also Monday, lithography and wafer bonding tool provider EV Group said it established a relationship with ASSID to jointly develop high-volume manufacturing processes for 3-D IC integration applications. The organizations will attempt to extend temporary bonding and de-bonding processes to support chip-to-wafer bonding with higher levels of topography (up to 600 microns thick)—a critical step in ramping 3-D IC technology to volume production, according to EV Group.
ASSID is developing enhanced 3-D integration, assembly and interconnection technologies to enable the heterogeneous integration of different chip functionalities within a single packaged device.
ASSID was established in 2009 by Saxony to stop the erosion of semiconductor manufacturing development around Dresden. At the time, the Saxon government claimed that ASSID would be the first research institute in the world dedicated to R&D on back-end 3-D chip production.
Altatech (Montbonnot, France) said ASSID is using a single-wafer, multi-chamber AltaCVD 300 system to deposit conformal dielectric liners inside TSVs to build 3-D system in package devices. The TSVs being filled have aspect ratios up to 10:1 and diameters as small as 10 microns, according to Altatech.
"We’re achieving excellent quality in film conformality, uniformity and integrity at low processing temperatures below 400°C," said M. Jürgen Wolf, manager of Fraunhofer IZM-ASSID, in a statement.
Also Monday, lithography and wafer bonding tool provider EV Group said it established a relationship with ASSID to jointly develop high-volume manufacturing processes for 3-D IC integration applications. The organizations will attempt to extend temporary bonding and de-bonding processes to support chip-to-wafer bonding with higher levels of topography (up to 600 microns thick)—a critical step in ramping 3-D IC technology to volume production, according to EV Group.
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resistion
10/11/2011 6:52 PM EDT
No industry involvement means faster, more independent development but harder for acceptance.
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docdivakar
10/20/2011 3:48 PM EDT
Seems like a good start at 10um TSV. The article leaves out subsequent metallization / via fill capability of ASSID. I also would like to know the planarization of the metal fill in the TSV.
MP Divakar
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