IMEC, Panasonic show reconfigurable IC win

LEUVEN, Belgium – Reconfigurable logic, often touted as a nice-to-have feature to help cope with late-changing standards and to improve time-to-market, is starting to show clear advantages in area efficiency over conventional ASIC logic, according to research organization IMEC.

Liesbet van der Perre, program manager for "Green Radio" projects at IMEC, told a press gathering here that the complexity of regional modes and frequencies being shown in areas such as LTE communications and digital broadcast television are now making reconfigurability a "must-have" feature for reasons of area efficiency and cost. This is not least because modern systems must also support host of legacy standards, as well as more demanding new ones.

IMEC has worked towards green 4G radios with three Asian partners, Renesas, Samsung and Panasonic, as well as EDA partners Cadence, Synopsys and Target Compiler Technologies, using its line of Scaldio analog front ends and Cobra digital baseband. The later includes the ADRES reconfigurable parallel processor.

IMEC has now developed a reconfigurable receiver that supports the DVB-T, ISDB-T and ATSC digital video broadcasting standards. The design is at the virtual silicon stage and is aimed at a 40-nm general purpose process tapeout with TSMC, said van der Perre. The receiver is realized using co-optimization of both algorithmic implementations of the standards and of IMEC's ADRES processor which is redubbed BOADRES in this implementation.

"We now have vector units and scalar units. It is much more heterogeneous." The Boadres is dual-core implementation that adds thread-level parallelism to data-level parallelism, van der Perre said. For low-energy considerations the design features no large register files or buses, with register-level communications all done point-to-point. The design has a customizable instruction set that has been matched to the C-input DRESC parallelizing compiler. hereas the old ADRES was implemented in 90-nm and could run at 400-MHz clock frequency, the BOADRES in 40-nm should clock 700-MHz, she added.

As area efficiency is one of the most important factors that determine the final cost of commercial chipsets, competitive area efficiency is crucial for SDR baseband solutions and the optimizations for television were realized in the context of Panasonic's partnership in the green radio research program.

Van der Perre declined to give the area reduction achieved compared with a multi-ASIC benchmark they had been provided but described it as "drastic."

And the commonality of many of the algorithms between standard such as Wi-Fi, WiMax and digital television and cellular communications mean that both an IEEE 802.11n inner receiver and a cat-4 LTE receiver can run real time on the same architecture.

Van der Perre then proceeded to describe a mobile internet radio architecture based on BOADRES with a derivative of the Scaldio front-end providing a flexible AFE for carrier frequencies below 10-GHz and 60-GHz transceiver as second interface.


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