Perfecting the 3-D chip

You’ve heard the hype: The foundation of semiconductor fabrication will be transformed over the next few years as multistory structures rise up from dice that today are planar. After almost a decade of major semiconductor engineering efforts worldwide aimed at making the structures manufacturable, three-dimensional ICs are poised for commercialization starting next year—several years behind schedule.

Chip makers have spent the past several years perfecting the through-silicon vias that will interconnect 3-D ICs. Now that TSVs have been honed for 2-D tasks, such as transferring data from the front side of a planar chip to bumps on the flip side, the stage is set for 3-D ICs using stacked dice.

Last winter’s International Solid-State Circuits Conference featured “almost-3-D” chips, such as Samsung’s much-publicized 1-Gbit mobile DRAM (with a planned ramp to 4 Gbits by 2013). Samsung’s 2.5-D technique mates stacked DRAM dice with TSVs and microbumps atop a system-in-package. 

Samsung announced this wide-I/O 1-Gbit DRAM for smartphones and tablets at this year's ISSCC. The device uses 3-D TSVs mated to microbumps. SOURCE: Samsung Click on image to enlarge.

A second major 2.5-D success is expected this fall, when Xilinx promises to deliver a multi-FPGA solution using a packaging process that interconnects four side-by-side Virtex-7 FPGAs with microbumps on a silicon interposer. Taiwan Semiconductor Manufacturing Co. is making the silicon interposer, which redistributes the FPGAs’ interconnections using TSVs that mate to copper balls on a substrate package using a controlled-collapse chip connection (C4). TSMC promises to make its seminal 2.5-D-to-3-D transition technology available to its other foundry customers next year.

Xilinx uses TSVs combined with controlled-collapse chip connection solder bumps to mount four FPGAs on a TSMC-made silicon interposer. SOURCE: Xilinx Click on image to enlarge.

The surprise 3-D IC announcement for 2011, however, comes from IBM, which recently confided that it was already secretly mass-producing full-fledged 3-D ICs on high-volume mobile consumer devices, albeit using low-density TSVs. As a result of the experience it has gained, IBM now claims to have identified the remaining engineering hurdles to 3-D and says it expects to surmount them in 2012.

“The era of the one-trick pony is gone,” said Bernard Meyerson, vice president of research at IBM (Armonk, N.Y.). “You are not going to win the 3-D performance battle if you rely solely on materials, or chip architecture, or networking, or software and integration. To win at 3-D, you need to use all these resources together at the most holistic level possible.”

Last month, IBM announced it had approached 3M about creating a designer material—akin to asking for “a really tall short person,” as Meyerson described it—that would solve the last remaining engineering hurdle to 3-D ICs: overheating. 3M’s job is to create an underfill material that fits between stacked dice and is an electrical insulator (like a dielectric) but is more thermally conductive than silicon (like a metal). 3M promises to have its miracle material ready for commercialization in two years.

“Right now we have trials ongoing, and by 2013 we want to have a formula in place that is ready for widespread commercialization,” said Ming Cheng, technical director of 3M’s Electronics Markets Materials Division (see sidebar, last page).

Some analysts are not convinced the IBM-3M joint development effort will necessarily put the pair ahead in 3-D ICs.

“3M is making an underfill material that will address the thermal issues for 3-D stacking,” said Françoise von Trapp, principal analyst for advanced packaging technologies at the MEMS Investor Journal. “While that’s definitely one of the remaining limitations needing to be addressed before 3-D ICs go to volume production, I don’t think anyone believes it’s the final key to unlocking the remaining issues for 3-D stacks.”