Even IBM’s claimed lead in 3-D IC production is not without its challengers. In fact, Tezzaron Semiconductor (Naperville, Ill.) has been offering 3-D IC design services for its tungsten TSV process for several years. Tezzaron’s FaStack process can create 3-D chips from heterogeneous dice on wafers as thin as 12 microns. It features wide I/O for stacked DRAMs with submicron interconnections as dense as 1 million TSVs per square millimeter.
Serial entrepreneur Zvi Or-Bach, a past winner of an EE Times ACE Award for Innovator of the Year, argues that 3-D IC designers need to move beyond TSVs to ultrahigh-density monolithic 3-D. That’s not a surprising view for Or-Bach, whose latest role is president and CEO of IP developer MonolithIC 3D Inc. (San Jose, Calif.). Startups like BeSang Inc. (Beaverton, Ore.) claim to be fabricating prototypes of TSV-free monolithic 3-D memory chips that could debut in 2012.
The state of the art today, however, is 3-D chip stacking using TSVs, and every major semiconductor company is working on the technology. “IBM is pushing the envelope, thinking beyond the current frame of things by partnering with 3M. However, every advance made by IBM in 3-D will unleash the creativity in competitors like Samsung, Intel and TSMC, all of which have independent development efforts under way for 3-D ICs,” said market watcher Richard Doherty, director of The Envisioneering Group (Seaford, N.Y.).
The techniques for making 3-D ICs are not new; rather, the current efforts focus on refining them. For instance, many CMOS imagers today use TSVs to bring pixel data from the front to the rear side of their substrate, and the idea of stacking chips itself dates back to early patents issued to transistor pioneer William Shockley circa 1958. Since then, many stacked-die configurations have been used—such as stacking a MEMS sensor atop an ASIC, or a small DRAM atop a processor core—but usually using wirebonding for interconnection.
Moving from wirebonds to TSVs allows interconnections to be denser. It also it frees designers from the tyranny of the rectangular “farm plot,” letting them design chip layouts more like circuit boards. Areas devoid of circuitry could be used for other structures, such as vertical interconnection buses or even chimneys for refrigerant gases. Heterogeneous 3-D stacked dice also offer a new level of integration, as whole systems can be combined into a single silicon brick.
“The most important thing that 3-D ICs bring is an opportunity to get away from the farm analogy, where every chip is divided up into adjoining rectangular neighborhoods that are fully populated,” said Doherty. “Instead of trying to use up all of the real estate on a chip, 3-D chip designers are going to start cutting out squares, triangles and circles [from dice] for vertical interconnect and to carry away heat.
“A lot of new ideas for chip design are being made possible by 3-D. Designers are going to have to think differently, since they can now mix their CPU, memory and I/O functions in novel ways that couldn’t be done when everything had to fit side-by-side on one postage stamp.”
The various semiconductor associations are all undertaking standards efforts for 3-D techniques. Semiconductor Equipment and Materials International has four groups working on 3-D IC standards. Its Three-Dimensional Stacked Integrated Circuits Standards Committee includes SEMI members Globalfoundries, Hewlett-Packard, IBM, Intel, Samsung and United Microelectronics Corp. (UMC), as well as Amkor, ASE, Europe’s Interuniversity Microelectronics Center (IMEC), Asia’s Industrial Technology Research Institute (ITRI), Olympus, Qualcomm, Semilab, Tokyo Electron and Xilinx.
Sematech, for its part, has established a 3-D Design Enablement Center. Participants include Altera, Analog Devices, LSI, ON Semiconductor and Qualcomm. Sematech also operates a 300-mm 3-D IC pilot line at the University of Albany’s College of Nanoscale Science and Engineering in New York state.
IMEC (Leuven, Belgium) is working with Cascade Microtech Inc. (Beaverton, Ore.) in the testing and characterization of 3-D ICs. And German research institute Fraunhofer IZM says it will be able to integrate processor, memory, logic, analog, MEMS and RF chips into monolithic 3-D ICs by 2014.
ITRI, based in Taiwan, sponsors a 3-D IC consortium that today has more than 20 members. Many of those participants are promising end-to-end 3-D IC foundry services starting as early as next year.
In September, at the 3-D IC Technology Forum held during Semicon Taiwan, Intel was reported to be working on stacked-die 3-D ICs (not to be confused with its FinFET trigate transistors, which are not intended for 3-D ICs). Also at Semicon, Elpida Memory (Tokyo) was reported to have made progress with Powertech Technology and UMC on a 2-Gbit DRAM that uses stacked DDR3 dice linked by high-density TSVs.
The Joint Electron Device Engineering Council is pioneering a Wide I/O standard for 3-D ICs that’s due by year’s end. The Jedec spec will support 512-bit-wide interfaces.
France’s CEA-Leti (Grenoble) is working with STMicroelectronics and silicon interposer maker Shinko Electric Industries Co. to smooth the 2.5-D to 3-D IC transition. The group is prototyping devices now at a 300-mm wafer fabrication facility and promises commercial designs as early as 2012.
Longer-range efforts are under way in Europe’s CMOSAIC program to find novel methods of cooling monolithic 3-D chip stacks beyond 2013. The four-year project involves IBM Zurich, École Polytechnique Fédérale de Lausanne (Paris) and the Swiss Federal Institute of Technology Zurich.