Sidebar: IBM, 3M pair off for 3-D
IBM + 3M = 3-D ICs. It’s a catchy formula. “Somewhere in the middle of those initials, 3M has the technology platforms to make 3-D work,” said Bernard Meyerson, vice president of research at IBM (Armonk, N.Y.)
After years of research into each of the component technologies needed to enable 3-D ICs, IBM decided there was a missing material so important that it cut a deal with 3M to create it. The key remaining obstacle to 3-D ICs, according to IBM, is an underfill material that can do double duty as an electrical insulator and a thermal conductor, wicking away heat from hot spots. IBM aims to use the material in conjunction with microfluidic channels containing refrigerants on 3-D structures.
“3M has the skills to meet the really disparate requirements for a 3-D IC adhesive,” said Meyerson. “You want infinite thermal conductivity in the adhesive, but you also want the electrical conductivity to be zero.”
The worst constraint, according to Meyerson, is that the coefficient of thermal expansion for the adhesive must match that of the metal used for the interconnect; otherwise, the adhesive will break the metallization when it heats up.
“Thermal conductivity, electrical conductivity and thermal expansion are all related, not to mention brittleness. It’s what we call an overconstrained system.”
Ming Cheng, technical director of 3M’s Electronics Markets Materials Division, said 3M “is essentially a materials company with the capability to tune the properties of adhesives and polymers to meet even these conflicting specifications. Our adhesive will be a combination of different types of polymers, oligomers and monomers, along with the necessary feelers and adhesion promoters that meet IBM’s specifications.”
According to 3M, it has not yet been decided whether the jointly developed 3-D IC adhesive will be sold to other chip makers. But in the past IBM has made a practice of licensing its key patents even to competitors.
In this artist's rendering, IBM demonstrates how future
3-D ICs would stack processors, memory and photonic networking onto separate layers of the same silicon brick. SOURCE: IBM
Click on image to enlarge.
3M also has experience with the fluids that are used today to cool hot spots in rack-mounted computers, and those fluids could soon flow through microfluidic channels cut into 3-D ICs. “Even if you have the perfect adhesive, it may be necessary to remove heat from the internal layers of a tall stack,” said Meyerson. “A microchannel-cooled radiator halfway through the stack could take out a bunch of heat from the middle of a silicon brick.”
Said Cheng: “Our Fluorinert electronic liquids are currently used to help cool equipment in data centers—mostly servers and hard drives—but with IBM we will also be exploring the liquids’ use to help cool 3-D ICs.”
Beyond perfecting the processing technologies to interconnect stacked dice and keep them cool, designers must consider the tide of data that will be streaming out of 3-D ICs, according to IBM. Photonics will become an integral part of 3-D ICs to handle the voluminous I/O.
“Electronic data transmission today can consume up to 50 percent of a chip’s power. Photonics is vastly more efficient in watts per bit and, for that reason, will be essential for 3-D ICs,” said Meyerson. “We’ll need lasers, modulators and detectors right in the 3-D IC stack.”
The work with IBM was announced just recently, but 3M has been working on 3-D solutions for some time. Earlier this year, in fact, 3M announced a technology for handling wafers destined for 3-D stacks. The company’s wafer-supporting-system (WSS) simplifies the handling of wafers that have been thinned for stacking.
WSS “first bonds the thin wafer to glass with a temporary adhesive so that the glass can support the wafer during bonding,” said Cheng. “After the two wafers are stacked, debonding allows the glass [carrier] to be removed.”
By 2013, 3M and IBM promise an end-to-end process ready for widespread high-volume commercialization of heterogeneous stacks of processor, memory, mixed-signal, networking and I/O chips formed into silicon skyscrapers as high as 100 chips per stack. — R. Colin Johnson