It's got to stack up
The high read-write cycling endurance of RRAM is a key advantage of the technology over flash for which the endurance tends to reduce with scaling. For flash it can be as low as 10^4 cycles at 22-nm.
Hewlett Packard Co., which is working with Hynix, recently reaffirmed its goal of seeing so-called memristor products by the end of 2013 (see HP, Hynix plan to launch memristor memory in 2013
However, Altimime said he would be surprised to see that happen. "You push floating gate as far as it will go and that means 3-D. For 16-nm floating gate 3-D BiCS is available," he said referring to Toshiba's proposed option for a 3-D NAND flash memory.
Most memory makers have a proposed 3-D flash structure such as P-BiCS (pipe-shaped bit cost scalable) from Toshiba and SanDisk, TCAT (terabit cell array transistor) from Samsung, VSAT (vertical stacked array transistor) and VG (vertical gate).
By integrating monolithically 8, 16 or 32 layers of such non-volatile memory elements the planar design rules can be relaxed or at least maintained at the present leading-edge of about 25-nm and still exceed 2-D memory sizes. Indeed, Altimime makes the point that planar design rules may have to be relaxed to achieve acceptable yields. The more layers there are and the greater the complexity the lower the yield. So company engineering work will focus on optimizing the balance of technology, critical dimensions, monolithic integration and multi-die integration, said Altimime.
"It takes three to four years from R&D to product. We base our timelines on engineering so we believe that stacked flash comes first and then RRAM is a possibility."
Related links and articles:
Novel structures, litho tricks finesse NAND scaling
HP, Hynix plan to launch memristor memory in 2013
IEDM: Hynix takes NAND to 15-nm
IMEC claims ReRAM filament breakthrough
Micron gains as floating-body firm closes