News & Analysis
TSMC's R&D chief sees 10 years of scaling
Dylan McGrath
10/25/2011 2:45 PM EDT
SANTA CLARA, Calif.—The path is clear for continued semiconductor scaling using FinFETs for the next decade, down to the 7-nm node, according to Shang-Yi Chiang, senior vice president of R&D at foundry giant Taiwan Semiconductor Manufacturing Co.
Beyond 7-nm, the most pressing challenges to continued scaling will come from economics, not technology, Chiang said in a keynote address at the ARM TechCon event here Tuesday (Oct. 25).
Chiang (above) said he has faith that the semiconductor industry will solve technical hurdles associated with moving past 7-nm over the next decade, but acknowledged that the new technologies might make volume manufacturing of chips with critical dimensions smaller than 7-nm cost prohibitive.
"From node to node, we have found the wafer price has increased much more than previous nodes," Chiang said.
In another ARM TechCon keynote later, Chi-Ping Hsu (right), senior vice president of R&D at in EDA vendor Cadence Design Systems Inc.'s Silicon Realization Group, presented data on dramatic cost increases associated with moving from the 32/28-nm node to the 22/20-nm node. The amount of money invested by the semiconductor industry in process R&D, for instance, jumped from $1.2 billion at 32/28 to between $2.1 billion and $3 billion at 22/20, Hsu said. Design costs for a chip jump from $50 million to $90 million at 32-nm to $120 million to $500 million at 22-nm, Hsu said.
At the 32-nm node, a chip needs to sell about 30 to 40 million units to recoup the costs associated with it, Hsu said. At the 20-nm node, the "breakeven" point jumps to between 60 and 100 million units, Hsu said.
FinFETs are three-dimensional transistors in the early stages of being adopted by chip makers. Intel Corp., which refers to its 3-D transistor technology as "tri-gate," is expected to begin sampling 22-nm chips with 3-D transistors later this year.
Chiang said the 20-nm node will be the last generation at which the semiconductor industry can possibly use a planar transistor. "After that, it will run out of steam," Chiang said.
Beyond 7-nm, the most pressing challenges to continued scaling will come from economics, not technology, Chiang said in a keynote address at the ARM TechCon event here Tuesday (Oct. 25).
Chiang (above) said he has faith that the semiconductor industry will solve technical hurdles associated with moving past 7-nm over the next decade, but acknowledged that the new technologies might make volume manufacturing of chips with critical dimensions smaller than 7-nm cost prohibitive.
"From node to node, we have found the wafer price has increased much more than previous nodes," Chiang said.
In another ARM TechCon keynote later, Chi-Ping Hsu (right), senior vice president of R&D at in EDA vendor Cadence Design Systems Inc.'s Silicon Realization Group, presented data on dramatic cost increases associated with moving from the 32/28-nm node to the 22/20-nm node. The amount of money invested by the semiconductor industry in process R&D, for instance, jumped from $1.2 billion at 32/28 to between $2.1 billion and $3 billion at 22/20, Hsu said. Design costs for a chip jump from $50 million to $90 million at 32-nm to $120 million to $500 million at 22-nm, Hsu said. At the 32-nm node, a chip needs to sell about 30 to 40 million units to recoup the costs associated with it, Hsu said. At the 20-nm node, the "breakeven" point jumps to between 60 and 100 million units, Hsu said.
FinFETs are three-dimensional transistors in the early stages of being adopted by chip makers. Intel Corp., which refers to its 3-D transistor technology as "tri-gate," is expected to begin sampling 22-nm chips with 3-D transistors later this year.
Chiang said the 20-nm node will be the last generation at which the semiconductor industry can possibly use a planar transistor. "After that, it will run out of steam," Chiang said.
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crwilliams
10/25/2011 4:33 PM EDT
As I recall, there are about 4 exp 9 atoms of silicon per meter. That's 4 per nanometer.
A 7 nanometer line therefore covers about 28 silicon atoms. With levels of doping several orders of magnitude smaller, it's difficult to see how 7 nanometer features can function as effective and reliable semiconductors.
What's the magic ingredient that I missed?
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mike655mm
10/25/2011 5:44 PM EDT
I don't know about your numbers but it was because of this that Intel developed their High-K process for 45nm back in 2007
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GroovyGeek
10/25/2011 9:10 PM EDT
Less and less reliance on doping in the channel.
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pixies
10/28/2011 4:03 PM EDT
Intel has demonstrates 15 nm transistors in the lab several years ago. 7 nm is the width of the gate, not the channel. Even if it is for the channel, it is a three dimension thing, there are more than 1000 atoms for the cross-section.
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resistion
10/25/2011 6:03 PM EDT
Ten silicon nitride lattice constants ~8 nm.
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OSAT guy
10/26/2011 2:22 AM EDT
For the face saving sake, these big first tier companies just refuse to admit the chip scaling is almost dead, may be 22nm/20nm is the last generation of posssible mass production,I would say 28nm may be even the one as last node for MP. The article has already hinted that it is technically achievable, but not viable economically! Well, he have to say so otherwise he is out of the job.
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wilber_xbox
10/26/2011 7:10 AM EDT
well not quite true that the scaling is dead. FinFET is quite an amazing technology which will push the scaling to 7nm and beyond that there are options available but there is no clear winner.
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resistion
10/26/2011 8:08 AM EDT
Tunnelling has to be considered below 10 nm. It's not that helpful.
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Alpha_mo_YF
10/26/2011 2:40 AM EDT
At the 32-nm node, a chip needs to sell about 30 to 40 billion units to recoup the costs associated with it, Hsu said. At the 20-nm node, the "breakeven" point jumps to between 60 and 100 million units, Hsu said.
the 32-nm node--30 to 40 billion units
the 20-nm node--jumps to between 60 and 100 million units
billion & million units ,billion should be million? what's wrong here??
--EEtimes editor,please answer this question.
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dylan.mcgrath
10/26/2011 2:45 AM EDT
Sorry. This was an error which has now been corrected. Thanks for bringing it to my attention.
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Alpha_mo_YF
10/26/2011 2:47 AM EDT
BIG deal: For sixth paragraph
billion should be million? what's wrong here??
--EEtimes editor,i appreciate that you could please answer this question.
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dylan.mcgrath
10/26/2011 12:09 PM EDT
@Alpha_mo_YF- Again, this was an error, for which I apologize. Thank you very much for bringing it to my attention. It has now been corrected.
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wilber_xbox
10/26/2011 7:12 AM EDT
To absorb the higher cost of the development, collaboration seems to be the only choice.
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Hephaestus
10/26/2011 12:08 PM EDT
Collaboration and competition are the yin and yang of R&D. The former conserves resources but suppresses true new innovation. The latter is where the (unforeseen) technology revolutions come from but can become prohibitively expensive and end up inhibiting new development by killing cross-hybridization of ideas between groups. Like biological evolution, it is a messy and nonlinear process.
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yalanand
11/4/2011 2:20 AM EDT
So will FinFETs revolutionize the tools industry as well. What will happen to conventional layout,schematic,spice tools. How different is FinFETs from the existing FET's and how will it affect the tool vendors ?
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