Intel details 22-nm Ivy Bridge at ISSCC

SAN JOSE, Calif. – Intel will describe as many as four designs using its new 22-nm process technology with 3-D transistors, including one of its next-generation Ivy Bridge processors at the International Solid-State Circuits Conference in February.

Intel will discuss an entry-level desktop or notebook processor from its upcoming Ivy Bridge family. It uses four of its IA-32 cores, a graphics-processing core, memory and a PCI Express controller, all built with 22-nm 3-D transistors.

Intel gave its first public disclosure of Ivy Bridge at the Intel Developer Forum in September. The company claims the 22nm process with its tri-gate FinFET transistors delivers twice the performance or half the power compared to its 32 nm process. Four Taiwan ODMs showed prototype ultrabooks using Ivy Bridge chips at IDF.

Three other ISSCC papers will discuss pieces of Intel processors made in its new 22-nm process. The company will describe a 22nm digital phase-locked loop (PLL) and a reconfigurable clock-generation core based on the PLL. The 22-nm core consumes 3mW at 1V and operates at 3.2 GHz in low power mode.

In a separate paper, Intel will talk about a SIMD vector graphics core that uses 22-nm technology to get a nine-fold increase in energy efficiency over its prior parts. Another Intel paper will describe a 32-nm Intel IA-32 processor core that consumes just 737 mW at 1.2V while running at 915MHz.

Researchers from China's Fudan University will show an even more power efficient part at ISSCC. Their 16-core processor made in 65-nm CMOS consumes just 320mW at 1.2V while running at 800 MHz.

At the high-end, Fujitsu will describe the K computer, currently ranked as the world's fastest supercomputer on the Top 500 list. The first version of the system used 548,000 Sparc64 VIIIfx cores and a proprietary Tofu interconnect to hit 8.162 petaflops. An upgraded version with more cores recently became the first system to surpass 10 petaflops.