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iniewski

12/8/2011 10:10 AM EST

thank you @agk...static body bias would just shift VTH permanently so it will ...

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agk

12/8/2011 4:31 AM EST

DDC 43 nm needs body bias either fixed or dynamic to make the transitor faster ...

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IEDM: SuVolta transistor operates down to 0.4-V

Peter Clarke

12/7/2011 7:28 AM EST

Engaged with foundries at 28-nm

Jeff Lewis, senior vice president of marketing and business development, confirmed that SuVolta is engaged with multiple foundries working on 28-nm and expected results at that process node to emerge in 2012.

The DDC technology matches well with existing infrastructures including existing system-on-chip (SoC) design layouts, existing design schemes such as body bias control, and existing manufacturing tools, said Lewis.

SuVolta argues that one reason that the scaling of supply voltage stopped at the 130-nm node was because of random dopant fluctuation (RDF) in the implanted dopants in the transistor channel. RDF results in variation in threshold voltage (VT) between different transistors on a chip.

Successful reduction of RDF has been reported using two exotic structures, ETSOI and Tri-Gate – a FinFET technology. However, both ETSOI and FinFET technologies are complex, making them difficult to match with existing design and manufacturing infrastructures.DDC achieves tight control of dopants in layers of epitaxial silicon growth to define a thin channel at the start of the manufacturing process.

Thereafter the process is a conventional bulk CMOS process but without the need to inject dopants using ion implantation. According to the Fujitsu paper intra-die VT variation is reduced by half through the use of DDC compared with Fujitsu's non-DDC 65-nm CMOS.




The DDC (deeply depleted channel) transistor shows tight control of dopant concentration and depletion depth. It improves VT matching and is additive to ten years of developments in strain engineering. The no-, low- and high-dopant concentrations are achieved through multiple growth phases of epitaxial silicon prior to device fabrication. The regions are not shown to scale. Source: SuVolta.



The cross sectional transmission electron micrograph (TEM) shows the transistor fabricated on a planar bulk silicon structure. Source: SuVolta

SuVolta entered the Silicon 60, EE Times' list of emerging startup companies at version 11.0 in October 2010. The latest edition of the Silicon 60 is version 12.5, which is the subject of a detailed technology and employment digital edition which can be accessed via http://e.ubmelectronics.com/Silicon60/index.html

Related links and articles:

www.suvolta.com

News articles: 

SuVolta describes low power transistor

EE Times updates ‘Silicon 60’ list of emerging startups

Stealthy Low­Power Play Has a Legion of High­Profile Backers Paid





iniewski

12/7/2011 12:26 PM EST

SuVolta continues to come up with very exciting announcements...but how one develops very advanced transistor structures without access to a state-of-the-art fab?...was the work done at Fujitsu's facilities? Kris

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peter.clarke

12/7/2011 12:39 PM EST

@kris

I don't think it is made explicit exactly where the work was done. But I think it is safe to assume it was done at a Fujitsu wafer fab or research fab where they can run the 65-nm CMOS manufacturing process.

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iniewski

12/7/2011 12:45 PM EST

thank you Peter...low VDD operation requires low VTH...but a textbook challenge of lowering VTH is increased leakage current (it is an exponential increase), perhaps someone from SuVolta can explain how they have overcome that challenge...Kris

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peter.clarke

12/7/2011 3:05 PM EST

My understanding is that the text book challenge to increased leakage current in bulk CMOS is because of the depth of the transistor channel

Like FinFET and FDSOI, DDC has a shallow and tightly controlled channel. Unlike FinFET DDC can support multiple VTs easily.

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agk

12/8/2011 4:31 AM EST

DDC 43 nm needs body bias either fixed or dynamic to make the transitor faster and less leakier.

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iniewski

12/8/2011 10:10 AM EST

thank you @agk...static body bias would just shift VTH permanently so it will not solve anything...how would dynamic bias work? low VTH when in operation and high VTH when powered off?...I thought the same trick is used in many processes (like SOI for example)...Kris

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