FDSOI less 'risk' than FinFETs, says SOI body

LONDON – The SOI Industry Consortium, and industry body for proponents for silicon-on-insulator manufacturing, reckons it's got fresh evidence in favor of using the fully-depleted version of its technology FDSOI instead of the FinFET style of manufacturing favored by Intel.

The consortium said that collaborative research recently completed by STMicroelectronics, IBM, ARM, Globalfoundries and other semiconductor companies had confirmed equivalent performance to FinFETs at 28-nm and 20-nm nodes but with a simpler manufacturing process.

The joint research was performed by using an FD-SOI process to fabricate 28nm chips. Test results on these chips were in line with predictions from computer-based models previously developed to benchmark FD-SOI device performance, confirming the models' reliability, the consortium said.

"Not only do the benchmarking results show that FD-SOI can deliver the power and performance of FinFET as early as the 28-nm and 20-nm technology nodes, but FD-SOI's ability to accommodate planar architectures presents much lower manufacturing risk than FinFET," said Horacio Mendez, executive director of the SOI Industry Consortium.

"This makes FD-SOI an easy-to-implement solution for cost-sensitive applications that require high performance and low power consumption in standby and active modes, including mobile electronics such as smart phones and tablet computers."

The simulations, which are now believed to hold true, show the feasability of running all digital device designs, including SRAMs, at Vdd voltages down to 0.6-V, the consortium said.

The SOI Industry Consortium did not address directly the issue of its starting cost disadvantage, from the use of SOI wafer. But said that a study published in July 2011 had showed that the cost of fabricating 20-nm SOC devices on FD-SOI wafers will be comparable to using planar bulk transistors - and more economical than using FinFETs.

Nor did the SOI Industry Consortium pass any comment on the process technology being proposed by SuVolta Inc. (Los Gatos, Calif.) which is claimed to have many of the same planar benefits of FDSOI without the expense of starting with SOI wafers.

Back in May 2011 Intel released details of its 22-nm process called 1270 that uses FinFETs. The first wafers were due to come out of the D1D research fab in Oregon with volume production due to start at the F32 fab in Arizona in the second half of 2011.


Related links and articles:

www.soiconsortium.org

News articles:

IEDM: SuVolta transistor operates down to 0.4-V

Fully-depleted SOI has cost advantage in processing

Intel tips 22-nm tri-gate (FinFET), but mobile is MIA