TSMC goes it alone with 3-D IC process

BURLINGAME, Calif. – TSMC will try to go it alone with an integrated 3-D chip stacking technology as its only offering for future customers. The approach makes commercial sense for TSMC, but some fabless chip designers said it lacks technical merit and limits their options.

3-D chip stacks are seen as a strategic new direction in chip design at a time when progress is becoming more difficult in the traditional scaling of semiconductor process technology. However, foundries, packaging houses and integrated chip makers are still debating how to address the technical challenges making 3-D stacks.

TSMC claims its approach will be simpler, cheaper and more reliable than using multiple foundries, packaging houses and other partners. It is focused on creating so-called through-silicon vias (TSVs) early on in the process, then adding packaging capabilities to its fabs.

The Taiwan chip maker made 3-D test chips for about five companies including Xilinx which used Amkor as a packaging partner. These "first wave" 3-D customers will be able to continue using external partnerships if they choose, "but for new customers we have this one proposal, one [integrated] solution," Doug Chen-Hua Yu, a senior R&D director at TSMC, told EE Times.

"Some, but not all our customers want us to work with other partners, but many customers like our approach very much," Yu said.

Yu pitched the integrated approach in a presentation at a 3-D technical conference here. Using a single foundry, reduces shipping that can crack the thin wafers needed for 3-D ICs and reduces confusion of who is liable for a broken product. TSMC also believes it can lower costs by eliminating unneeded steps at lower capital equipment costs than packaging houses, Yu said.

In a Q&A afterwards, packaging analyst Jan Vardaman asked Yu how TSMC would develop the test, assembly and substrate expertise paclkaging companies have today.

"This new proposal is only two or three quarters old because we worked with many customers in this area and we found out [reliability issues] had become much worse, more risky and complicated," Yu said. "Someone has to come forward to assume the responsibility and take on the challenges--this is a new ball game, and the old way of doing business is out of date, I'm afraid," he said.

Xilinx plans to continue using a mix of foundries and packaging houses such as TSMC and Amkor to make its so-called 2.5-D chips such as the Virtex 2000T announced earlier this year.

"In general, the fabless industry would like more degrees of freedom," Ivo Bolsens, chief technology officer of Xilinx told EE Times. "I don’t see any technical reason against any particular design flows," he added.

Analysts noted TSMC will face plenty of competition and may be forced into being more of a team player.

"TSMC said they want to do everything," said Jim Feldhan of Semico Research. "That’s very gallant of them, but we need the rest of the industry to step up so that these processes are well adopted and understood," he said.

"TSMC makes a very compelling case [for going it alone] but others won't lie down or go away--there's a lot of money in play here," said Jeff Perkins, President of Yole Inc.