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docdivakar
The WideIO standard has been RELEASED! You can download it here free ...
docdivakar
Thermal management will always be a challenge when the horizontal real estate is ...
First 3-D IC spec set for release
By MP Divakar, PhD
12/16/2011 12:43 PM EST
SAN FRANCISCO -- JEDEC which announced a broad set of 3D IC standards development earlier in 2011 is all set to release what is touted as the first 3D IC interface standard which will be out in late December of this year (or some time in January 2012).
At GSA's 3D IC task group meeting held earlier this week, Intel's Ken Shoemaker presented more details of the WideIO Memories where more details of the electrical and mechanical interface were shared.
JEDEC has a head start in releasing 3D IC standards –its standard for reliability of 3D chip stack with through-silicon-via (TSV), JEP158, was released in Nov 2009 . With the soon to be released WideIO standard, it appears it is maintaining that lead, for now among the standards generation efforts of SEMI, Sematech and Si2.
The industry consensus is that LPDDR2 will run out of bandwidth before WideIO memories are commercially available. LPDDR3 (which is a linear evolution of LPDDR2) is expected to fill this gap by supporting higher operating frequencies while maintaining power efficiencies of LPDDR2. The 800MHz LPDDR3 will feature 50% more bandwidth than a 533MHz LPDRR2 while retaining the equivalent pin count as LPDRR2.
Figure 1. WideIO Positioning
Source: Sophie Dumas, ST-Ericsson, Mobile Memory Forum, June 2011; more mobile memory presentations here
Developed by JEDEC task group JC42.6 which began its work in December 2008, WideIO is explicitly a 3D standard for now (2.5D interface is on the future development roadmap) combining logic and DRAM in the same package to reduce interconnect capacitance. The soon-to-be released specification calls for a maximum 4-dice stack of memory cube that can interface to a logic SoC with a maximum target package size of 10x10x1mm.
JC42.6 for WideIO specifies the logic to memory interface (LMI) leveraging the work of two JEDEC committees –JC42.6 (Low Power DRAMs) and JC11 which has a long-standing in mechanical standardization of chip packages. The mechanical interface between memory logic and memory has been generically named as Micro Pillar Gate Array (MPGA, link).
The interconnect method between logic and memory is not specified and can be micro bumps, micro pillars, etc. The standard also specifies boundary scan to test interconnect continuity, post-assembly direct-access memory test, location of thermal sensors in the memory dice, and the exact mechanical layout of the chip-to-chip interface.
The standard does not specify the memory-to-logic interconnect design or method of assembly. The exact location of the interconnect on either the memory or the logic chip is not specified as are the dimensions and locations of TSVs. The thickness of memory and logic chips, assembly methods and post-assembly test methods are all unspecified.
JC42.6 for WideIO specifies the logic to memory interface (LMI) leveraging the work of two JEDEC committees –JC42.6 (Low Power DRAMs) and JC11 which has a long-standing in mechanical standardization of chip packages. The mechanical interface between memory logic and memory has been generically named as Micro Pillar Gate Array (MPGA, link).
The interconnect method between logic and memory is not specified and can be micro bumps, micro pillars, etc. The standard also specifies boundary scan to test interconnect continuity, post-assembly direct-access memory test, location of thermal sensors in the memory dice, and the exact mechanical layout of the chip-to-chip interface.
The standard does not specify the memory-to-logic interconnect design or method of assembly. The exact location of the interconnect on either the memory or the logic chip is not specified as are the dimensions and locations of TSVs. The thickness of memory and logic chips, assembly methods and post-assembly test methods are all unspecified.
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resistion
12/17/2011 11:49 AM EST
Dr. Divakar, thanks for the article.
TSV pitch 40 nm? Should be um?
With DRAM price always under pressure, adapting TSV is quite difficult, due to extra cost.
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docdivakar
12/17/2011 4:17 PM EST
40um! Yes, you are correct, I had used the Word symbol font which got mangled it would appear!
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resistion
12/17/2011 11:52 AM EST
Samsung's wide io took up more than 20% area for just 2 layers, it seems adding layers requires more wide I/O area.
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Rchandta1
12/17/2011 1:26 PM EST
With low latency for the memory access, does the TSV diminishes need for cache?
This article does not address resolving thermal issue. I think it might be the limited factor for the performance or bandwidth.
Yes, cost might inhibit adoption in applications like cell, for it should not be any problem for high performance servers.
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docdivakar
1/5/2012 4:36 PM EST
Thermal management will always be a challenge when the horizontal real estate is a premium and one is constrained by cost for adding solution in the vertical dimension!
Dealing with thermal management is an application issue that the JEDEC standard recognizes but steers clear of making specific recommendations. It is up to the design teams.
MP Divakar
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kinnar
12/19/2011 9:06 AM EST
Does it mean that after the standardization of the 3D IC, memories packages will get converted in to cube forms instead of stripe packages? If the interface is planner as depicted in the figure, why it is called 3D IC?
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docdivakar
1/5/2012 4:12 PM EST
Well, packages have been growing in the 3-rd dimenions for several years now -incarnations like Package-on-Package (PoP) are shipping in millions of volumes. Amkor recently announced crossing 100Million PoPs.
TSV's are one way to start stacking bare dice to realize a product. 3DIC stacked products look much like existing Semi packages while internally their construction will be a lot different.
The interface defined by the JEDEC WideIO standard lets one create memory+controller product by stacking. It doesn't dictate the dia of TSV's but provides guidelines for locating interconnects between memory, logic and other functions via TSV's.
I hope this helps.
MP Divakar
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KHummler
12/19/2011 9:26 AM EST
Please note that SEMATECH is not a standards body. SEMATECH actively works to forge industry consensus (e.g. through our wiki site: wiki.sematech.org), but does not define or publish 3D standards.
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Sanjib.Acharya
12/20/2011 10:21 AM EST
Is there any illustration showing what kind of packages would be used for the 3D ICs?
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docdivakar
1/5/2012 4:24 PM EST
Sanjib, a good majority of the 3DIC using TSV's are & will be substrate-based packages, BGA being the most common. The biggest advantage of stacking using TSV's is by delivering much more functionality (not to mention the storage) in the same form factor.
MP Divakar
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Astronut
12/20/2011 3:55 PM EST
This is not the *first* 3D-IC standard! Look here:
http://www.3d-ic.org/standards.html
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docdivakar
1/5/2012 4:22 PM EST
Perhaps the title should have reflected TSV-based 3D IC standard. You are right, 3DIC standards have been around a while now. Wirebonded memories have shipped in Billions!
MP Divakar
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docdivakar
1/6/2012 10:29 AM EST
The WideIO standard has been RELEASED! You can download it here free (registration required):
http://www.jedec.org/standards-documents/results/jesd229
MP Divakar
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