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docdivakar
What is discomforting is that the product announcements utilizing stacked 3DIC ...
Sematech identifies top tech challenges to 3-D ICs
12/20/2011 1:53 PM EST
SAN FRANCISCO—Semiconductor technology research consortium Sematech's 3D Enablement Center (3DEC), together with the Semiconductor Industry Association (SIA) and Semiconductor Research Corp. (SRC) , has identified the top technical challenges for new "killer" applications to enable future development of heterogeneous 3-D integrations beyond mobile wide I/O DRAM, Sematech said Tuesday (Dec. 20).
Discussions with expert university professors and users, including the 3D EC member companies and SRC, have identified heterogeneous computing, memory, imaging, smart sensor systems, communication switches, and power delivery/conditioning as some of the potential future killer applications, Sematech said.
The common technical challenges associated with these applications have been prioritized: lowering the cost of 3-D architectures, system/architecture pathfinding, generic heterogeneous multi-die stack testing issues and thermal management, according to Sematech said.
"Tackling the common challenges of next generation applications is critical for acceleration of the broad adoption of 3-D ICs," said Dan Armbrust, Sematech's president and CEO, in a statement. "Sematech’s 3D Enablement Center's goal in the next phase of this broad based collaborative program is to provide the enabling infrastructure to address these common technical challenges."
Following the introduction of the wide I/O DRAM, further research and development of 3-D IC technology will be driven by high demand, high volume applications that continue to demonstrate the benefits of 3D integration, including lower power consumption, higher performance, increased functionality and lower cost, according to Sematech.
Since January, Sematech's 3DEC has spearheaded the development of standards and specifications for 3-D, according to Sematech. To prepare for the future 3-D integration ICs and systems, the 3D EC is identifying three-to-five-year window killer applications and the common technical challenges they pose to smoothly extend 3D technology beyond mobile wide I/O DRAM, Sematech said.
"The development of 3-D integration technology is at an inflection point," said Brian Toohey, president of the SIA. "The industry has experienced the benefits of collaboration in many efforts, from the semiconductor roadmap to finding the next switch. This evolving partnership aims at taking 3-D integration technology to the next step—to fully realize its significant potential for semiconductor manufacturing and design."
Sematech's 3DEC is a cooperative effort among members of the program, the SIA, and the SRC. Since its launch in December 2010, the center has focused on enabling industry-wide ecosystem readiness for cost-effective TSV-based 3-D stacked IC solutions.
Discussions with expert university professors and users, including the 3D EC member companies and SRC, have identified heterogeneous computing, memory, imaging, smart sensor systems, communication switches, and power delivery/conditioning as some of the potential future killer applications, Sematech said.
The common technical challenges associated with these applications have been prioritized: lowering the cost of 3-D architectures, system/architecture pathfinding, generic heterogeneous multi-die stack testing issues and thermal management, according to Sematech said.
"Tackling the common challenges of next generation applications is critical for acceleration of the broad adoption of 3-D ICs," said Dan Armbrust, Sematech's president and CEO, in a statement. "Sematech’s 3D Enablement Center's goal in the next phase of this broad based collaborative program is to provide the enabling infrastructure to address these common technical challenges."
Following the introduction of the wide I/O DRAM, further research and development of 3-D IC technology will be driven by high demand, high volume applications that continue to demonstrate the benefits of 3D integration, including lower power consumption, higher performance, increased functionality and lower cost, according to Sematech.
Since January, Sematech's 3DEC has spearheaded the development of standards and specifications for 3-D, according to Sematech. To prepare for the future 3-D integration ICs and systems, the 3D EC is identifying three-to-five-year window killer applications and the common technical challenges they pose to smoothly extend 3D technology beyond mobile wide I/O DRAM, Sematech said.
"The development of 3-D integration technology is at an inflection point," said Brian Toohey, president of the SIA. "The industry has experienced the benefits of collaboration in many efforts, from the semiconductor roadmap to finding the next switch. This evolving partnership aims at taking 3-D integration technology to the next step—to fully realize its significant potential for semiconductor manufacturing and design."
Sematech's 3DEC is a cooperative effort among members of the program, the SIA, and the SRC. Since its launch in December 2010, the center has focused on enabling industry-wide ecosystem readiness for cost-effective TSV-based 3-D stacked IC solutions.
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docdivakar
12/28/2011 5:20 PM EST
What is discomforting is that the product announcements utilizing stacked 3DIC have all been from big companies like Samsung and Micron. The so called partnerships do not encourage smaller and/or startups to play thru product innovations. This has to change in the 3DIC game, otherwise, it is destined to become the play of a few big companies.
MP Divakar
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