LONDON – French research institute CEA-Leti has announced the launch of a 3-D packaging platform and service that provides industrial and academic partners with what it describes as a "mature" process for the production of 3-D interconnected products and projects.
The "Open 3D" offering from CEA-Leti (Grenoble, France) includes 3-D design, layout, interconnection, TSV formation, component assembly, reliability testing and final packaging.
The 3-D packaging is done at the Minatec campus in Grenoble by Leti teams. It is fully operational on 200-mm wafers with acceptance of 300-mm wafers due to become operational in 2012. The technologies on offer include formation of through silicon vias (TSVs), microbumping of wafers, redistribution of layers (RDL), under-bump metallurg, temporary bonding, thinning and debonding. The Open 3D approach is applicable to active wafers populated with die and to passive wafers characterized to perform the interconnect function of a silicon interposer.
The service is expected to address a wide range of markets including life sciences, medical electronics, aeronautics and space, consumer applications, defense and security, or fundamental research.
The service allows customers to achieve proof of concept with a small quantity of wafers or move to prototyping with a larger quantity of wafers but is based on a limited set of process technologies to ensure moderate costs, short cycle times and to meet the needs of initial customers, Leti said.
"Our partners will include laboratories, universities and international research institutes as well as fabless chip companies and niche market manufacturers and integrators," said Laurent Malier, CEO of Leti.
CEA-Leti has worked with ST-Ericsson, STMicroelectronics and Cadence Design Systems Inc. on the creation of Wioming
, a 3-D stacked application processor for smartphones that makes use of wide I/O DRAM memory. Leading foundry Taiwan Semiconductor Manufacturing Co. Ltd. is developing its own 3-D IC packaging system under the name COWOS which stands for chip on wafer on substrate.
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