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Lattice has shipped more than 20 million programmable mixed-signal devices
Clive Maxfield
2/14/2012 6:20 AM EST
Lattice Semiconductor has announced that it has shipped more than 20 million programmable mixed signal devices. Fast-growing, worldwide adoption is spread over key mixed-signal device families including the Lattice Power Manager II, the newly released Platform Manager, and ispClock families. Lattice programmable mixed-signal devices are used in a range of applications from low-cost solid state drives to complex high-end telecommunication infrastructure cards.
The Power Manager family was the first programmable mixed-signal device family created by Lattice. Responding to customer need for integration and true “management,” Lattice defined the industry’s first PLD-based flexible power management system: a fully integrated device providing hot-swap controller, voltage supervisor, reset generator, and sequencer ICs into a single chip solution that is significantly less expensive and more accurate than other solutions.
As circuit board control plane functionality became increasingly popular among the company’s broad customer base, Lattice developed the Platform Manager family, extending the functionality of power management to include both power and digital management within a single-chip solution. All Power Manager II functions are supported in Platform Manager devices. Integration allows the Power Manager device to have a quick response time that enables the fault logging application to capture the initial error condition. Fault logging that is implemented with discrete ICs or a microprocessor is typically too slow to catch the initial event, making troubleshooting difficult.
As the complexity of SoCs continues to increase, efficient clock management becomes more difficult. In response to this challenge, Lattice created the ispClock family, a mixed-signal standard clock net solution device that fully integrates clock generators and clock distribution, providing a low-cost programmable skew solution. A single chip product, the ispClock device from Lattice replaces an assortment of zero delay buffers, fan-out buffers, termination resistors, delay lines and serpentine clock trace layouts. Lattice’s ispClock devices can be programmed in-system to generate multiple clock frequencies, compensate each output for differences in clock trace lengths, precisely match trace impedances and drive clock nets with different signaling requirements.
“We used all of the resources available on the Power Manager POWR1014A device, from the on-board ADC to the MOSFET drivers,” said Wayne Kuei, Research and Development Director, Advantech Co., Ltd. “The Power Manager device helped us achieve our goals of reduced cost, stability, functionality and simplified component sources, resulting in a simpler and more cost effective BOM.”
"Customers are discovering that they can easily increase the reliability of their systems while reducing cost,” said Shyam Chandra, Lattice Manager of Mixed Signal Solutions. “System reliability no longer needs to suffer from marginally designed power and platform management because of time and cost constraints. Our integrated solutions resolve many system problems that can often be traced back to an overlooked power management detail.”
All mixed-signal product families are supported by customer proven development kits and reference designs enabling fast, easy product development.
Click Here for more information about Power Manager devices; Click Here for information on the new Platform Manager devices, visit; Click Here for information on the ispClock devices; Click Here for details on the Hercules development kit; and Click Here for information on Platform Manager Development kits.
Software support
Designs for the Power Manager II, ispClock and Platform Manager devices are implemented using the Windows-based Lattice PAC-Designer Software version 6.1 that is available for download free of charge from the Lattice website (Click Here for more information)
If you found this article to be of interest, visit Programmable Logic Designline where you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
The Power Manager family was the first programmable mixed-signal device family created by Lattice. Responding to customer need for integration and true “management,” Lattice defined the industry’s first PLD-based flexible power management system: a fully integrated device providing hot-swap controller, voltage supervisor, reset generator, and sequencer ICs into a single chip solution that is significantly less expensive and more accurate than other solutions.
As circuit board control plane functionality became increasingly popular among the company’s broad customer base, Lattice developed the Platform Manager family, extending the functionality of power management to include both power and digital management within a single-chip solution. All Power Manager II functions are supported in Platform Manager devices. Integration allows the Power Manager device to have a quick response time that enables the fault logging application to capture the initial error condition. Fault logging that is implemented with discrete ICs or a microprocessor is typically too slow to catch the initial event, making troubleshooting difficult.
As the complexity of SoCs continues to increase, efficient clock management becomes more difficult. In response to this challenge, Lattice created the ispClock family, a mixed-signal standard clock net solution device that fully integrates clock generators and clock distribution, providing a low-cost programmable skew solution. A single chip product, the ispClock device from Lattice replaces an assortment of zero delay buffers, fan-out buffers, termination resistors, delay lines and serpentine clock trace layouts. Lattice’s ispClock devices can be programmed in-system to generate multiple clock frequencies, compensate each output for differences in clock trace lengths, precisely match trace impedances and drive clock nets with different signaling requirements.
“We used all of the resources available on the Power Manager POWR1014A device, from the on-board ADC to the MOSFET drivers,” said Wayne Kuei, Research and Development Director, Advantech Co., Ltd. “The Power Manager device helped us achieve our goals of reduced cost, stability, functionality and simplified component sources, resulting in a simpler and more cost effective BOM.”
"Customers are discovering that they can easily increase the reliability of their systems while reducing cost,” said Shyam Chandra, Lattice Manager of Mixed Signal Solutions. “System reliability no longer needs to suffer from marginally designed power and platform management because of time and cost constraints. Our integrated solutions resolve many system problems that can often be traced back to an overlooked power management detail.”
All mixed-signal product families are supported by customer proven development kits and reference designs enabling fast, easy product development.
Click Here for more information about Power Manager devices; Click Here for information on the new Platform Manager devices, visit; Click Here for information on the ispClock devices; Click Here for details on the Hercules development kit; and Click Here for information on Platform Manager Development kits.
Software support
Designs for the Power Manager II, ispClock and Platform Manager devices are implemented using the Windows-based Lattice PAC-Designer Software version 6.1 that is available for download free of charge from the Lattice website (Click Here for more information)
If you found this article to be of interest, visit Programmable Logic Designline where you will find the latest and greatest design, technology, product, and news articles with regard to programmable logic devices of every flavor and size (FPGAs, CPLDs, CSSPs, PSoCs...).
Also, you can obtain a highlights update delivered directly to your inbox by signing up for my weekly newsletter – just Click Here to request this newsletter using the Manage Newsletters tab (if you aren't already a member you'll be asked to register, but it's free and painless so don't let that stop you [grin]).
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