News & Analysis
Comment
green_is_now
time, 4th dimension, or it ain't 3D
dleske
Intel confirmed as foundry for second FPGA startup
Dylan McGrath
2/21/2012 12:01 AM EST
SAN FRANCISCO—Programmable logic startup Tabula Inc. confirmed Tuesday (Feb. 21) that Intel Corp. will manufacture the firm's 22-nm 3PLD products using Intel's 3-D tri-gate transistors.
Tabula (Santa Clara, Calif.) becomes the second programmable logic startup confirmed to be using Intel's Custom Foundry division for foundry work. In October 2010, Achronix Semiconductor Corp. announced that Intel would build its 22-nm FPGAs.
Intel dabbled in the foundry and ASIC markets for years. But the firm exited the ASIC business years ago and has never been considered a major foundry player. Some analysts have speculated since the Achronix deal was announced that the world's No. 1 chip vendor wanted to increase its presence in the foundry space, which is dominated by Taiwan Semiconductor Manufacturing Inc. (TSMC). Last year, the Reuters news service reported that Intel executives said, if given the opportunity, the company would happily manufacture higher volumes of chips for major companies such as, hypothetically, Apple Inc.
Like Achronix, Tabula is a relatively small programmable logic startup trying to compete in a market segment dominated by Xilinx Inc. and Altera Corp. Tabula's manufacturing volume at 22-nm will be extremely low in comparison to Intel's own products. Because there is a premium placed on leading-edge process technology in high-end programmable logic, which both Tabula and Achronix offer, it is likely that the idea of working with Intel is especially attractive to them.
"We felt early on as we looked at what Intel was doing on this technology node that there would be some synergy between our product and Intel's technology," said Dennis Segers, Tabula’s CEO.
Rumors of a Tabula-Intel foundry relationship have been circulating for nearly a year.
Intel announced last May that it tri-gate transistors, which the company had been developing for years, would form the basis of the company's 22-nm process technology. The technology was originally supposed to be in volume production by late last year, but recent reports have indicated that Intel's 22-nm processors, codenamed Ivy Bridge, won't be in volume production until June.
Tabula, which operated in semi-stealth mode for years before March 2010, when the company publicly detailed its Spactime three-dimensional programmable logic architecture, which the company says will enable a new class of devices, 3PLDs, that offer the capability of an ASIC, ease of use of an FPGA and price points suitable for volume production.
According to Tabula, the Spacetime programmable fabric delivers a balanced architecture with shorter interconnects than traditional FPGAs and the ability to clock the entire fabric—logic, DSP, memory, and interconnect—at the same frequency. To do that, the Spacetime architecture uses time as a third dimension to reduce the number of components needed to implement a function and can deliver smaller, higher performance chips, according to the company.
Tabula uses TSMC to build its 40-nm ABAX products, which are currently in volume production and can operated at clock sppeds of 1.6 GHz. Seggers said the relationship with TSMC would continue on the 40-nm products. "We continue to work with TSMC on that product and we have an ongoing relationship with TSMC," Seggers said. "We have great respect for TSMC. They are the best in the world at what they do."
Seggers declined to reveal when Tabula's next-generation 22-nm devices would be in volume production. Details about the agreement with Intel were also not disclosed.
Tabula (Santa Clara, Calif.) becomes the second programmable logic startup confirmed to be using Intel's Custom Foundry division for foundry work. In October 2010, Achronix Semiconductor Corp. announced that Intel would build its 22-nm FPGAs.
Intel dabbled in the foundry and ASIC markets for years. But the firm exited the ASIC business years ago and has never been considered a major foundry player. Some analysts have speculated since the Achronix deal was announced that the world's No. 1 chip vendor wanted to increase its presence in the foundry space, which is dominated by Taiwan Semiconductor Manufacturing Inc. (TSMC). Last year, the Reuters news service reported that Intel executives said, if given the opportunity, the company would happily manufacture higher volumes of chips for major companies such as, hypothetically, Apple Inc.
Like Achronix, Tabula is a relatively small programmable logic startup trying to compete in a market segment dominated by Xilinx Inc. and Altera Corp. Tabula's manufacturing volume at 22-nm will be extremely low in comparison to Intel's own products. Because there is a premium placed on leading-edge process technology in high-end programmable logic, which both Tabula and Achronix offer, it is likely that the idea of working with Intel is especially attractive to them.
"We felt early on as we looked at what Intel was doing on this technology node that there would be some synergy between our product and Intel's technology," said Dennis Segers, Tabula’s CEO.
Rumors of a Tabula-Intel foundry relationship have been circulating for nearly a year.
Intel announced last May that it tri-gate transistors, which the company had been developing for years, would form the basis of the company's 22-nm process technology. The technology was originally supposed to be in volume production by late last year, but recent reports have indicated that Intel's 22-nm processors, codenamed Ivy Bridge, won't be in volume production until June.
Tabula, which operated in semi-stealth mode for years before March 2010, when the company publicly detailed its Spactime three-dimensional programmable logic architecture, which the company says will enable a new class of devices, 3PLDs, that offer the capability of an ASIC, ease of use of an FPGA and price points suitable for volume production.
According to Tabula, the Spacetime programmable fabric delivers a balanced architecture with shorter interconnects than traditional FPGAs and the ability to clock the entire fabric—logic, DSP, memory, and interconnect—at the same frequency. To do that, the Spacetime architecture uses time as a third dimension to reduce the number of components needed to implement a function and can deliver smaller, higher performance chips, according to the company.
Tabula uses TSMC to build its 40-nm ABAX products, which are currently in volume production and can operated at clock sppeds of 1.6 GHz. Seggers said the relationship with TSMC would continue on the 40-nm products. "We continue to work with TSMC on that product and we have an ongoing relationship with TSMC," Seggers said. "We have great respect for TSMC. They are the best in the world at what they do."
Seggers declined to reveal when Tabula's next-generation 22-nm devices would be in volume production. Details about the agreement with Intel were also not disclosed.
|
|
|
|
|
Navigate to related information
resistion
2/21/2012 3:58 AM EST
As a foundry, Intel's offerings are high end FPGAs only at this point? Will Intel be able to support 22 nm foundry work as it ramps up its own products?
Sign in to Reply
dylan.mcgrath
2/21/2012 11:01 AM EST
I don't know if that is the only thing Intel is offering, foundry wise. It may be that that is the only segment at this point that is willing to pay Intel's premium. As far as its own ramp, Intel has enough employees that I don't think a couple small foundry customers will be a distraction. However, there is some speculation that Intel is having difficulty with the 22-nm ramp, hence the delays.
Sign in to Reply
JJ600
2/22/2012 11:23 AM EST
This is more like Intel needs business collaboration in the embedded applications. Solely foundry business for this customer (and Achronix also) won't help to boost Intel's revenue.
Sign in to Reply
KB3001
2/21/2012 11:37 AM EST
I am not sure they want to deal with bigger players to be honest, especially in areas where their own processors compete.
Sign in to Reply
iniewski
2/21/2012 9:40 AM EST
Sounds like a great scoop for Tabula. Have they released their re-configurable on the fly FPGA products? Kris
Sign in to Reply
dylan.mcgrath
2/21/2012 11:03 AM EST
Tabula has 40-nm 3PLDs available. Are they configurable "on the fly?" I'm not sure about that.
Sign in to Reply
KB3001
2/21/2012 11:35 AM EST
I think dynamic reconfiguration sits at the heart of Tabula do.
Sign in to Reply
iniewski
2/21/2012 2:50 PM EST
They use time multiplexed logic...Kris
Sign in to Reply
JJ600
2/22/2012 11:28 AM EST
You can imagine that this is like PC with disc cache memory. Theoretically, it could have much larger gate count under a small footprint. However, it affects the performance greatly, also 1.6GHz clock generates a lot of more power than expected, during this "on-the-fly" reconfigurations.
Sign in to Reply
kinnar
2/21/2012 1:29 PM EST
It is good that Tabula is dealing with both the Giant Foundries TSMC and Intel this way it will be able to have access to the latest manufacturing technology and the advantage of the experienced manufacturers. Altera and Xilinx will have to notice the presence of this small company coming up. By the way any clue about the manufacturing foundry of Altera and Xilinx products?
Sign in to Reply
iniewski
2/21/2012 2:48 PM EST
Altera has been working TSMC since 1993
http://www.altera.com/corporate/about_us/foundry/abt-tsmc-partnership.html
UMC used UMC for a while but recently switched to Samsung and TSMC
http://www.eetimes.com/electronics-news/4087890/Xilinx-confirms-Samsung-TSMC-in-UMC-out-at-28-nm
Sign in to Reply
dylan.mcgrath
2/21/2012 6:07 PM EST
I think Kris meant to say "Xilinx used UMC for a while..." At 40-nm, I think Xilinx uses both UMC and Samsung. At 28, it's TSMC and Samsung.
Sign in to Reply
iniewski
2/21/2012 10:20 PM EST
thank you Dylan, yes, obviously Xilinx
Sign in to Reply
sharps_eng
2/21/2012 6:52 PM EST
I still struggle with Tabula's concept; although I think I can see why they are going for the fastest (22nm) process they can get.
Serializing (which is time-multiplexing by another name) requires the hardware to have spare speed capacity (your pixel clock runs faster than your frame rate, for an extreme example), and if the hardware could run at full speed in parallel mode then it will out-run any multiplexed solution. The only exception is if there is a bottleneck, like free memory bus cycles becoming available because a CPU is busy, this allows pipelining, but the sidelined hardware must be running, doing something useful, while it is switched out, and it must preserve its state, otherwise it is simply redundant, inefficiently implemented hardware.
You can't re-use registers for multiple tasks unless you preserve state or switch only at stateless or minimum-state nodes in the execution flow, and that is a complex compiler function which is extremely difficult to map to applications efficiently.
The above holds true whatever level of logic granularity you work at; you can only get a net gain from serialization if there is inefficiency to be exploited, and I am not sure Tabula have shown where that inefficiency lies, exactly.
I will have to read further...
Sign in to Reply
Chief Startegy Officer, SCI
2/21/2012 8:19 PM EST
This Intel getting into "foundry" business was been told/advised by a former marketing director of TSMC. Same foresight were given on IDMs providing "foundry/ASIC" services to Design Houses. It had been coming true since 2008, e.g. Apple using SS to make A5, QCOMM using SS to get BB chips, ....etc.
He also predicted trend and actions that those capable companies would do and how landscape would change over time for next 5-10 yrs.
TSMC lost him and he was doing great in investment community.
Sign in to Reply
hm
2/21/2012 8:43 PM EST
It will be nice to see Apple and Intel working closely for 22nm and 18 nm nodes and delivering wonderful consumer products.
Sign in to Reply
iniewski
2/21/2012 10:21 PM EST
why is Apple suddenly in this story???
Sign in to Reply
dylan.mcgrath
2/21/2012 11:00 PM EST
Good question. There is no foundry relationship between Apple and Intel. The Reuters article from last year was about Intel execs saying they would be glad to get the Apple business if it was available to them. It is not, at this point. And I know many in the industry say that despite those comments, Intel actually would not want to go down that road.
Sign in to Reply
eewiz
2/22/2012 11:03 AM EST
True. why wud intel fab A5/A6 for apple? That wud kill Intels own mobile CPU line.
Sign in to Reply
iniewski
2/21/2012 10:26 PM EST
To @sharps_eng: I think Tabula's concept is quite different from what you are describing...I think it works like this (someone correct me if I am wrong, I am just guessing): you get piece of data to chew, you do something with it and send it away...next you get another piece but this time you are supposed to process the data differently so your FPGA re-configures itself to provide that new function and here you go...and then the next piece of data comes etc...you can packet processing done this way quite efficiently but you need to be damn fast in re-configuring your FPGA...Kris
Sign in to Reply
KB3001
2/22/2012 5:29 AM EST
That's my understanding of it too, Kris. The configuration is time-multiplexed as you said above. A whole chip configuration context is loaded at very fast rates to allow for this. I guess your question above was about "partial" dynamic reconfiguration, which I am not sure they support.
Sign in to Reply
JJ600
2/23/2012 2:20 PM EST
Hi Kris, I like to emphasize the "damn fast in re-configuring your FPGA". Either the reconfiguation clock is very fast (1.6GHz?) or the system clock is very slow. For either case, this 3DFPGA burns much higher power than traditional FPGA's. No perfect solution here.
Sign in to Reply
abismuth
2/24/2012 7:14 PM EST
A useful way to think of this question of power consumption is to consider two identical functions. One implemented using 8 LUTs each operating at 200 MHz, and the second using only 1 LUT operating at 1.6 GHz. If interconnect capacitance were the same in both cases, then power consumption would be identical. Of course in a 3D device interconnects are shorter, so in fact there’s a power advantage for the second faster implementation.
Sign in to Reply
abismuth
2/22/2012 6:30 PM EST
Great discussion about how our Spacetime 3D architecture works.
If you are interested in knowing more about it you can read this very good article written by Tom Halfhill at Microprocessor Report: http://www.tabula.com/news/M11_Tabula_Reprint.pdf
If you have more questions you can also contact me directly or through our website (www.tabula.com).
Sign in to Reply
resistion
2/23/2012 12:28 AM EST
Wow, clever use of time as third dimension!
Sign in to Reply
dleske
2/25/2012 12:36 AM EST
Good description in the article - it makes a lot of sense.
Most logic is synchronously clocked. Your approach seems to keep the states latched (in the virtual wires) while the logic is reconfigured to process other signals.
The reduced wiring complexity by treating time and space routing as interchangeable is very clever.
This offers a level in between standard logic (with gates performing only one function, often idle) and microprocessors (gates being re-used for different functions over time, at lower program speeds).
Wishing you the best success with it!
Sign in to Reply
iniewski
2/22/2012 8:16 PM EST
thank you @abismuth, fascinating technology: "By storing multiple gate configurations on chip, Tabula’s devices can completely reconfigure their fabrics up to 1.6 billion times per second"
any chance someone from Tabula would be interested in presenting it at CMOS emerging technologies event to be held in Vancouver in July? (www.cmoset.com)...I am the conference chair...pls contact me at kris.iniewski@gmail.com
Sign in to Reply
green_is_now
12/19/2012 7:57 PM EST
time, 4th dimension, or it ain't 3D
Sign in to Reply