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EDACEO
No tools are required for extracting inductance. The Cyclos IP that is provided ...
jigneshshah
AMD, not ARM, first to use startup's low-power clock IP
Peter Clarke
2/21/2012 7:32 AM EST
LONDON – Advanced Micro Devices Inc. has achieved the first commercial implementation of resonant clock mesh technology licensed from startup company Cyclos Semiconductor Inc.
Cyclos (Berkeley, Calif.) said that the AMD (Sunnyvale, Calif.) has used the power-saving clock distribution technology in x86-compatible processor cores destined for inclusion in Opteron server processors and client Accelerated Processing Units (APUs). Cyclos engaged with processor technology licensor ARM Holdings plc in the early years of its existence driving an expectation that an ARM processor core would be the first commercial demonstration of the technology.
However it is AMD's Piledriver 64-bit core, which operates at up to and in excess of 4-GHz clock frequency, that represents the first volume production-enabled implementation of resonant clock mesh technology, Cyclos said. Piledriver, fabricated in a 32-nm CMOS process, employs the resonant clocking to reduce clock distribution power by up to 24 percent, while maintaining previous clock-skew targets, Cylos said.
The Cyclos resonant clock mesh technology employs on-chip inductors arranged to interact with the large capacitance of the clock signal distribution network to form an oscillating "tank circuit." The result is that Cyclos inductors and clock control circuits "recycle" the clock power instead of dissipating it on every clock cycle as conventional clock tree implementations do. The result is a reduction in total IC power consumption of up to 10 percent, Cyclos said.
Cyclos was founded in 2006 as a spin out of the University of Michigan. The company is now based in Berkeley, California with an office in Ann Arbor, Michigan. Cyclos licenses resonant clock mesh semiconductor IP, design automation tools, and provides consulting services for resonant clock mesh design. Cyclos announced a proof of concept processor implementation based on the ARM926EJ-processor in 2008 under the name "Project Elizabeth" along with the availability of design tool support.
"We were able to seamlessly integrate the Cyclos IP into our existing clock mesh design process so there was no risk to our development schedule," said Samuel Naffziger, corporate fellow at AMD, in a statement issued by Cyclos. "Silicon results met our power reduction expectations, we incurred no increase in silicon area, and we were able to use our standard manufacturing process, so the investment and risk in adopting resonant clock mesh technology was well worth it as all of our customers are clamoring for more energy efficient processor designs."
In the same statement, Linley Gwennap, principal analyst of The Linley Group, said: "This announcement proves that the Cyclos resonant clock mesh technology provides meaningful power savings in real-world products. We expect other processor designers to adopt the Cyclos technology in applications where power reduction is important."
The company is led by Marios Papaefthymiou, founder and president; Alexander Ishii, vice president of engineering; and Dan Ganousis, vice president of business development.
"We believe resonant clock mesh design will be a key enabler for GHz+ embedded processor IP blocks in next generation SoCs that also require ultra-low power consumption," said Papaefthymiou, in the company's statement.
Related links and articles:
www.cyclos-semi.com
News articles:
Resonant-clocked design tools target ARM core
AMD: New faces, new road maps, new focus
AMD seeks edge in Intel-ARM clash
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iniewski
2/21/2012 9:20 AM EST
Impressive Cyclos technology coming our of academia...congrats Marios! Kris
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KB3001
2/21/2012 12:52 PM EST
I wonder about the yield figure?
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EDACEO
2/21/2012 5:41 PM EST
Regarding yield, designers using resonant clock meshes have actually realized no measurable yield degradation ... in some cases yields actually improve. Bear in mind that more than half of the typical clock tree drivers are eliminated with a resonant clock mesh - so there are many less candidates for circuit failure on chip. Consider that a clock buffer defect in a clock tree design makes the device unusable as an entire branch of the tree is no longer functioning. Not so with clock meshes - one buffer failure does not affect the function of the clock mesh as all buffer outputs are shorted together.
Granted, there can be a small area increase by adding the on-chip inductors which would reduce yield slightly ... but real world experience has shown that it's basically a wash - yield improvement or degradation is not expected. Most design teams today are quite happy to accept a small yield penalty in exchange for 10% total power reduction anyways.
More info can be found on the FAQ page of our website at www.cyclos-semi.com. Or feel free to contact me at dan.ganousis@cyclos-semi.com and I can provide very detailed technical info for you.
Dan Ganousis
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Frank Eory
2/21/2012 8:50 PM EST
Considering that such a large percentage of chip power is dissipated in the clock trees, this is great stuff! Is it possible to extend the power savings beyond 10%?
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EDACEO
2/21/2012 9:37 PM EST
Frank - absolutely. As with any first time implementation of new technology, the approach was somewhat conservative. We believe savings as large as 20% are possible with more aggressive design and analysis.
Indeed, clock power is a large % of chip power. Most designers estimate the clock network consumes about 30-35% of overall power - so there is a significant advantage to implementing resonant clock meshes.
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RakeshPatel
2/23/2012 1:52 PM EST
How will it affect coarse and fine-grained clock-gating ?
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huohatika
2/24/2012 2:56 AM EST
Resonant circuits reminds of Tesla, you should study what he achieved. With the possibility to integrate inductors on chip, you could put Tesla tech in micro scale in your chips. What does this mean ? Well, howabout a chip that powers itself once started. When you are running out-of-juice from your electric car, plug in your new handset and keep on driving. It gives all the juice you need. Impossible! you say. Not at all, this tech already exists but only on bigger scale. Google for Kapanadze free energy, he shows videos of devices with outputs from 5 kW to 100 kW.
Nice thing about resonant circuits is that higher the frequency the more power you get and smaller size is needed. Inductor's ability to induce power in another inductor depends on the speed of swithing (squared), voltage (squared), and amperage. With GHz speeds you can get lots and lots of more power compared kHz speeds. The trick you need to learn is to make output part so that it does not affect input. This is all explained in Tesla's patents. As you have already made resonant clock mesh, this nut should be easy to crack.
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EDACEO
2/24/2012 4:43 PM EST
Rakesh - There actually is very little affect on clock gaters. From the clock mesh and below, traditional clock tree synthesis tools are used for "localized" clock gating/routing. The benefits of the near-zero clock skew mesh, along with a much smaller tree to balance, makes the existing CTS methodology continued to be used.
Also, it is thus still possible to insert "useful skew" using CTS tools as many designers have been doing on past generation devices.
Dan
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EDACEO
2/24/2012 4:51 PM EST
All -
I've gotten several questions privately that I thought I would share with the rest of you since they seemed common to many people.
1. No special libraries or processes are required. Cyclos RCMs work with standard PDKs and does not require inserting any special cells.
2. Reliability may actually be improved due to the reduction in metal migration potential in the clock distribution network. With RCMs, current flows bidirectionally between the inductors and the clock mesh, as opposed to clock trees where the charge flow is unidirectional.
3. Cyclos design utilities/scripts and RCM IP work in standard RTL/Verilog flows.
4. Coarse and fine dynamic frequency scaling is supported. Realize of course, as one reader pointed out, that the efficiency of the inductors/resonance falls off quickly with lower frequencies. The RCM will continue to operate but the power savings will be reduced at lower frequencies.
Thanks to all for your interest and again please feel free to contact me if you have any further questions or would rather comment in private.
Dan Ganousis
dan.ganousis@cyclos-semi.com
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jigneshshah
2/27/2012 5:51 PM EST
Do we need a special tool for extracting inductance.?
For clock network simulation can we use any spice tool?
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EDACEO
3/3/2012 4:03 PM EST
No tools are required for extracting inductance. The Cyclos IP that is provided has been characterized in your process and simulation/verification models are provided. Users don't have to extract inductance so no tools are required.
And yes, designing a resonant clock mesh is very SPICE simulation intensive. Fortunately many EDA vendors have produced new SPICE simulators that have much greater capacity and throughput - so it is possible to simulate/verify a resonant clock mesh in a reasonable/timely manner.
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