Cadence moves physical design software to 20-nm

LONDON – Cadence Design Systems Inc. has announced that the latest release of its Encounter software suite for RTL-to-GDSII design supports the 20-nm manufacturing process technology node.

The design, implementation and signoff flow was developed in collaboration with IP and foundry partners and enables more efficient SoC development, Cadence said.

Cadence did not say how much Encounter RTL-to-GDSII for 20-nm cost per seat nor whose 20-nm processes it supports.

The flow is based on a number of tools with such names as Encounter RTL Compiler, Encounter Test, Encounter ECO Designer, Encounter Digital Implementation System, Clock Concurrent Optimization (CCOpt), Encounter Timing System, Encounter Power System, Cadence QRC Extraction, Cadence Physical Verification System, and other design for manufacturing technologies.

The software has already been supplied to some customers. "The Cadence Encounter RTL-to-GDSII flow enabled us to achieve the chip performance and feature objectives of our 1-GHz ARM Cortex-A5 processor-based smartphone platform on time and with greater development efficiency," said Leo Li, president and CEO of Spreadtrum, in a statement issued by Cadence.


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