IMEC offers 14-nm dev kit, test chip to follow 2H12

LONDON – European research institute IMEC has announced that is has released an early-version process development kit for logic that is the industry's first PDK to address the 14-nm node, IMEC said.

The kit includes support for a number of technologies that are likely to be required at the 14-nm node including FinFET devices and extreme ultraviolet lithography. It contains device compact models, parasitic extraction, design rules, parameterized cells (p-cells), and basic logic cells, IMEC (Leuven, Belgium) said.

The 14-nm PDK was developed as part of IMEC's Insite collaborative research program, in which Altera Corp., Nvidia Corp. and Qualcomm Inc. have been reported to be participants. In a press release announcing the 14-nm PDK did not discuss which chip companies participate in the Insite program.

The PDK is being made available to IMEC's research partners and will be followed by incremental updates. IMEC and its partners are developing a 14-nm test chip using this PDK which is due to be released in the second half of 2012, IMEC said. IMEC operates a 300-mm research wafer fab that contains an EUV lithography stepper. It is one of very few facilities in the world that could attempt to produce a 14-nm test chip.

One of the main purposes of the PDK is to help companies to develop processes with FinFETs. These fin-shaped transistors that sit proud of the wafer surface have a larger drive per unit footprint and higher performance at low supply voltages compared with traditional planar technologies. Evolutions of the PDK are also expected to introduce the use of high-mobility channel materials. Such materials include germanium, compound semiconductor materials and graphene. The PDK includes support for both immersion- and EUV lithography, opening the way for a gradual transition from 193nm immersion to EUV lithography.

The production of a test chip in 2H12 will allow the physical measurement of performance and power consumption and the first testing of the device-, interconnect-, process- and litho assumptions.


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