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R_Colin_Johnson
The advanced semiconductor nodes are demanding that designers scrutinize the ...
EDA tool aims at 10-nanometer 3-D
R Colin Johnson
4/9/2012 6:47 PM EDT
PORTLAND, Ore.—Reaching the advanced semiconductor process nodes at 22-nanometer and beyond requires accurate three-dimensional (3-D) models of the proposed physical structures to obviate the need for repeated trial-and-error design cycles. In fact, the International Technology Roadmap for Semiconductors has designated modeling 3D physical structures as a "grand challenge" at advanced processing nodes.
One of the few tools capable of modeling the ultra-compact structures of FinFETs and other 3-D transistor structures is SEMulator3D, which was originally created by EDA software house Conventor Inc. (Cary, North Carolina) for MEMS designs, but which today is used almost exclusively for advanced semiconductor designs. IBM, for instance, has chosen SEMulator3D to design its FinFETs at the 22-nanometer node and beyond.
"SEMulator3D has helped IBM predict problems that otherwise would only have been found by subsequent testing and physical failure analysis," said David Fried, 22-nm chief technologist at IBM.
The latest iteration of SEMulator3D 2012 now supports 64-bit voxels (3-D pixels that can be filled with any semiconductor material) enabling ultra-accurate modeling of 3-D semiconductor structures at advanced processing nodes.
SEMulator3D can model the micro-electro-mechanical structures on the most advanced semiconductors such as this FinFET SRAM cells with a high-K metal gate.
"Voxels are 3-D versions of pixels—the sum total of all your voxels is your physical design," said Ken Greiner, architect and manager of SEMulator3D. "And now that they have 64-bit precision, it is possible to achieve extremely fine details for designs beyond the 28-nanometer node."
SEMulator 2012 also has fully automated the setting of boundary conditions for all process steps, thereby removing a previous barrier to accurate simulations of advanced node designs which are strongly affected by the rough edges that result from using 193-nanometer light to illuminate the 22-, 14-, and 10-nanometer masks being designed today.
Besides front-end designs, SEMulator3D is also finding uses in design-rule "brain storming," failure analysis and metrology for both semiconductors and MEMS, according to Coventor.
One of the few tools capable of modeling the ultra-compact structures of FinFETs and other 3-D transistor structures is SEMulator3D, which was originally created by EDA software house Conventor Inc. (Cary, North Carolina) for MEMS designs, but which today is used almost exclusively for advanced semiconductor designs. IBM, for instance, has chosen SEMulator3D to design its FinFETs at the 22-nanometer node and beyond.
"SEMulator3D has helped IBM predict problems that otherwise would only have been found by subsequent testing and physical failure analysis," said David Fried, 22-nm chief technologist at IBM.
The latest iteration of SEMulator3D 2012 now supports 64-bit voxels (3-D pixels that can be filled with any semiconductor material) enabling ultra-accurate modeling of 3-D semiconductor structures at advanced processing nodes.
SEMulator3D can model the micro-electro-mechanical structures on the most advanced semiconductors such as this FinFET SRAM cells with a high-K metal gate.
"Voxels are 3-D versions of pixels—the sum total of all your voxels is your physical design," said Ken Greiner, architect and manager of SEMulator3D. "And now that they have 64-bit precision, it is possible to achieve extremely fine details for designs beyond the 28-nanometer node."
SEMulator 2012 also has fully automated the setting of boundary conditions for all process steps, thereby removing a previous barrier to accurate simulations of advanced node designs which are strongly affected by the rough edges that result from using 193-nanometer light to illuminate the 22-, 14-, and 10-nanometer masks being designed today.
Besides front-end designs, SEMulator3D is also finding uses in design-rule "brain storming," failure analysis and metrology for both semiconductors and MEMS, according to Coventor.
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R_Colin_Johnson
4/9/2012 7:08 PM EDT
The advanced semiconductor nodes are demanding that designers scrutinize the physical structures they propose before they actually fab them. Experienced designers depend on their personal knowledge bases, but as design rules shrink increasingly odd-ball discontinuities are popping up, especially at the boundaries of 3D structures like FinFETs. Tools exist for simulating detailed 3D structures, but usually only in very small areas, since they are incredibly computationally intensive. As a result, MEMS tools like this one which make estimations that the detailed tools won't allow are becoming more popular for "what if" scenarios that allow designers the luxury of making educated guesses, then confirming their suspicions before they even their EDA toolset.
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