Laundry list of challenges
In his keynote, Halepete ran through a laundry list of challenges that are slowing time-to-market and straining profitability for chip designs.
“The time between getting our design files to the fab and getting first samples back has been growing over the last couple process nodes,” Halepete said. “Between the 40 and 28nm nodes it lengthened by maybe four to six weeks” due to more masks and process steps he said.
Getting to volume production can now take as much as three months longer than in past generations, he said. “But the Christmas and back-to-school selling seasons are not going to move for you,” he quipped.
“There’s no single silver bullet to solving time-to-market pressures, it’s about addressing a lot of small problems, one at a time,” he added.
For example, designers need formal verification tools that set up problem statements earlier in the process to shorten the time to fixing design errors. In addition, front-end and physical designers need to work together more closely to address timing closure problems, and tools need to increase designer productivity, he said.
“We had to increase the size of our physical design team thirty-fold [for 28 nm chips compared to 1994 levels], but we cannot do this again for the next generations without hiring all the physical design engineers in world,” he said.
Nvidia and Mentor worked for the last several months on a tool that could automate the process of selecting optimal locations for the placement of physical chip macros. The job currently takes 8 to 12 weeks of a chip designer’s time, Halepete said.
New process technologies are “running out of steam” in their ability to lower power because voltages are not decreasing significantly, he said. Thus the next wave of improvements in energy efficiency will come from tools that can suggest optimizations in logic and circuit designs.
“It’s hard for engineers to find more than half or two-thirds of these opportunities,” he said.
As the processes become more complex, defect probabilities are rising, driving up the cost per square millimeter of finished silicon. To counter the effect, Nvidia has tried to lower its tests costs which can make up as much as five percent of the cost of a chip.
The company is multiplexing test channels and running them at higher frequencies in an effort to reduce test time. It is also working with a third party on a laser probing system that can speed the process of finding a hardware flaw.
“Getting defect density down as quickly as possible is essential because the window to make money on products is fixed,” Halepete said.
For its part, Mentor is seeing tech hurdles spark a rise in sales of emulation and packaging tools.
“Emulation is hot for the whole industry because we passed the point this year where you can do a full chip simulation,” said Rhines. “What was a sleepy old field for 30 years has become a hot ticket in last two,” he said.
Separately chip packaging software that was “a negligible business a few years ago” is now on the rise as chip-in-package designs emerge with thousands of connections to route, Rhines said. In addition, Mentor has seen “strong interest” in tools for handling interposer and flip-chip designs for early 3-D chip stacks, he said.
“I need to pay attention to what new problems are coming up because that’s where the growth will be, even though the vast amount of EDA money goes into continuing existing technologies,” Rhines said.