News & Analysis
TSMC to offer only one process at 20-nm
Dylan McGrath
4/17/2012 10:40 PM EDT
SAN JOSE, Calif.—Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC) will offer only one process at the 20-nm node, a change from the multiple processes that the foundry giant has offered customers for the past several nodes, a TSMC executive said Tuesday (April 17).
Speaking at TSMC's annual technology symposium here, Shang-yi Chiang, executive vice president and co-chief operating officer at TSMC, said the firm might also offer an 18- or 16-nm process node after 20-nm if lithography technology is not available to make 14-nm devices cost effectively.
Chiang said the TSMC initially planned to offer two 20-nm processes, presumably a high performance process and a low-power process. Both processes would have featured high-k metal gate (HKMG) technology.
But, after some development, TSMC determined that there was not a noticeable performance difference between the two 20-nm processes, Chiang said. Because 20-nm linewidths are so small, approaching fundamental physical limits, there isn't much room for tweaking design rules to specify different gate lengths and other requirements, Chiang said.
TSMC offers four processes at the 28-nm node: a high performance process, a low power process, another low power process with HKMG and a high performance process geared for mobile applications.
TSMC expects its 20-nm HKMG process to be in production next year. In 2015, TSMC wants to commence production at the 14-nm node, adding FinFET 3-D transistors.
But the semiconductor industry is waiting on extreme ultraviolet (EUV) lithography, which has been delayed several times. To date, no power source has been developed to provide the power and stability necessary to enable volume production at sufficient throughput. Lithography tool vendor ASML Holding NV is working with several power source developers on the technology and has pledged to make available tools with sufficient throughput later this year for commercial chip production in 2013 and 2014.
But many in the industry remain skeptical that EUV will be available in time to support the aggressive roadmaps of TSMC and other leading-edge chip manufacturers. Chiang also noted that lithographers have made a great deal of progress on the 193-nm immersion lithography to the point where it could be a commercially viable alternative at 14-nm. However, Chiang said, 193-nm immersion might require triple-patterning on some layers and double patterning on many layers in order to achieve adequate image fidelity, which would make it too costly for volume production.
Chiang said TSMC is "thinking very carefully" about whether to offer an 18- or 16-nm process. "If we choose this node, we will have to offer it to customers for 10 years," Chiang said.
Speaking at TSMC's annual technology symposium here, Shang-yi Chiang, executive vice president and co-chief operating officer at TSMC, said the firm might also offer an 18- or 16-nm process node after 20-nm if lithography technology is not available to make 14-nm devices cost effectively.
Chiang said the TSMC initially planned to offer two 20-nm processes, presumably a high performance process and a low-power process. Both processes would have featured high-k metal gate (HKMG) technology.But, after some development, TSMC determined that there was not a noticeable performance difference between the two 20-nm processes, Chiang said. Because 20-nm linewidths are so small, approaching fundamental physical limits, there isn't much room for tweaking design rules to specify different gate lengths and other requirements, Chiang said.
TSMC offers four processes at the 28-nm node: a high performance process, a low power process, another low power process with HKMG and a high performance process geared for mobile applications.
TSMC expects its 20-nm HKMG process to be in production next year. In 2015, TSMC wants to commence production at the 14-nm node, adding FinFET 3-D transistors.
But the semiconductor industry is waiting on extreme ultraviolet (EUV) lithography, which has been delayed several times. To date, no power source has been developed to provide the power and stability necessary to enable volume production at sufficient throughput. Lithography tool vendor ASML Holding NV is working with several power source developers on the technology and has pledged to make available tools with sufficient throughput later this year for commercial chip production in 2013 and 2014.
But many in the industry remain skeptical that EUV will be available in time to support the aggressive roadmaps of TSMC and other leading-edge chip manufacturers. Chiang also noted that lithographers have made a great deal of progress on the 193-nm immersion lithography to the point where it could be a commercially viable alternative at 14-nm. However, Chiang said, 193-nm immersion might require triple-patterning on some layers and double patterning on many layers in order to achieve adequate image fidelity, which would make it too costly for volume production.
Chiang said TSMC is "thinking very carefully" about whether to offer an 18- or 16-nm process. "If we choose this node, we will have to offer it to customers for 10 years," Chiang said.
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daleste
4/17/2012 11:04 PM EDT
It looks like the shrink roadmap is getting to the end. The savings of the shrink may not be more than the additional cost of the process. It's been a great trip but there may be no more Moore.
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rick.merritt
4/18/2012 5:01 PM EDT
I agree that is the very significant subtext to the news: Semiconductor technology slow down ahead. Make sure you are buckled in as we prepare for the shift to 3-D ICs and/or whatever else comes next.
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resistion
4/18/2012 10:21 PM EDT
I guess we'll believe it for sure if Intel's 14 nm gets stuck.
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ScottenJ
4/18/2012 12:41 AM EDT
I didn't think TSMC was going FinFET until 14nm.
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dylan.mcgrath
4/18/2012 2:30 AM EDT
@ScottenJ- you are absolutely right. This was my mistake. I have corrected it.
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PV-Geek
4/19/2012 12:14 PM EDT
The solutions exist to continue the technology roadmap, but they bring increased layout restriction and cost. Here you see the increased layout restriction manifested in a single process offering and the increased cost manifested in widespread use of multi-pattering techniques at 14nm and below. This is exactly why 3D-IC is becoming a reality as it's high cost is now more in line with the higher cost of smaller nodes. I don't think you will see the roadmap stop as we all want increased functionality in new products. But what you might see is a slow down or even reversal in Moore's law as it has applied to the cost of consumer products. The iPad 10 may be as expensive as a small car, but you may buy it anyway.
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agk
4/20/2012 3:41 AM EDT
The decision made by TSMC will change the majority of the semiconductor devices market soon. Probably again TSMC will compete in 20nm.
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Oscar Law
4/20/2012 11:16 AM EDT
With the great success of 28nm technology, all the resource are pulled in for production ramp up, it is good choice to offer single process for 20nm generation. Moreover, it is required large amount of efforts for design service support, especially for LDE modeling. Therefore, it is not pure technology decision but also business consideration.
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resistion
4/25/2012 1:41 AM EDT
Would it be possible for 20 nm to become tsmc's intermediate node, so to speak, with 17 nm or 16 nm being the "real" next node?
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iniewski
5/3/2012 2:12 PM EDT
I think this might be possible @resistion...Every second generation is much stronger than intermediate versions...0.35um was very strong but 0.25um was weak, then 0.18um was very strong, 90nm so, so, 65nm was probably higher runner than 45nm...etc
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