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peter.clarke
Although, Intel did gain a lot of ferroelectric memory knowledge in their ...
cidbarca
Thanks resistion, I think I see now. The high-k dielectric's polarization isn't ...
Intel, Micron on sub 20-nm and insatiable thirst for memory
Sylvie Barak
4/18/2012 12:51 PM EDT
Breaking barriers
Crooke said that the real breakthrough was with the materials used, enabling the cells to fit together more easily in ways where they affect each other less.
"We've always beaten Moore's Law, really, when it comes to memory scaling," said Ghodsi, noting that innovation would not simply dry up after passing the 20-nm watermark.
"This partnership that Intel and Micron have brings together arrays of technical expertise; design, technology, material science. The partnership is unequaled in the industry today. And that's what allows us to continue and even surpass Moore's Law," Ghodsi said.
Being first is not without its challenges, however, though Hawk said these weren't a major factor.
"Whenever you move to the next generation you do have to deploy some new things and the industry is doing that right now," he said. It's kind of nice because we're the first to discover some of those things and I think that gives us a leg up when we use these products in systems," he added.
While the Intel/Micron partnership has been able to extend the life of floating gate design for NAND on the 20-nm node, the team is not yet certain when it might start move away from floating gate to a new design, or what that new design would look like.
"When you look out into the future you see problems that look like barriers but when you get closer they turn out to just be hurdles," said Crooke, noting that when people predicted the end of NAND, because of issues around wrapped floating gate, science had pushed through.

Ghodsi explained that one of the reasons people believed floating gate couldn't scale was because as the devices got smaller, the number of electrons able to be stored on that smaller area was lower.
"But what people don't realize is that the number of electrons is proportionate to the capacitive coupling and Micron's move to a planar cell increases the capacitance," he said, noting that this was exactly the reason high-k material was used.
"Increased capacitance increases the number of electrons on that floating gate. As a result it gives us that ability to take this further," he said adding, "there are always innovations that allow you to use the same basic structure."
The team is already working with a very small number of electrons.
"On 20-nm the difference between states between one of our cells is far less than 100 electrons," said Hawk, claiming there were only about 20.
"They're not that well behaved in small numbers, either," he added with a smile.
Well behaved or not, Micron and Intel seem to have managed to harness their technology better than any current competitors, and the team says to expect a lot more in the near future.
Crooke said that the real breakthrough was with the materials used, enabling the cells to fit together more easily in ways where they affect each other less.
"We've always beaten Moore's Law, really, when it comes to memory scaling," said Ghodsi, noting that innovation would not simply dry up after passing the 20-nm watermark.
"This partnership that Intel and Micron have brings together arrays of technical expertise; design, technology, material science. The partnership is unequaled in the industry today. And that's what allows us to continue and even surpass Moore's Law," Ghodsi said.
Being first is not without its challenges, however, though Hawk said these weren't a major factor.
"Whenever you move to the next generation you do have to deploy some new things and the industry is doing that right now," he said. It's kind of nice because we're the first to discover some of those things and I think that gives us a leg up when we use these products in systems," he added.
While the Intel/Micron partnership has been able to extend the life of floating gate design for NAND on the 20-nm node, the team is not yet certain when it might start move away from floating gate to a new design, or what that new design would look like.
"When you look out into the future you see problems that look like barriers but when you get closer they turn out to just be hurdles," said Crooke, noting that when people predicted the end of NAND, because of issues around wrapped floating gate, science had pushed through.

Ghodsi explained that one of the reasons people believed floating gate couldn't scale was because as the devices got smaller, the number of electrons able to be stored on that smaller area was lower.
"But what people don't realize is that the number of electrons is proportionate to the capacitive coupling and Micron's move to a planar cell increases the capacitance," he said, noting that this was exactly the reason high-k material was used.
"Increased capacitance increases the number of electrons on that floating gate. As a result it gives us that ability to take this further," he said adding, "there are always innovations that allow you to use the same basic structure."
The team is already working with a very small number of electrons.
"On 20-nm the difference between states between one of our cells is far less than 100 electrons," said Hawk, claiming there were only about 20.
"They're not that well behaved in small numbers, either," he added with a smile.
Well behaved or not, Micron and Intel seem to have managed to harness their technology better than any current competitors, and the team says to expect a lot more in the near future.
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iniewski
4/18/2012 7:29 PM EDT
If there is only 20 electrons difference left between two memory states there is not much hope that this technology will scale beyond 20nm process...time to employ spin instead of charge? Kris
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resistion
4/19/2012 11:19 AM EDT
So Micron is not getting on the 3D NAND train?
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cidbarca
4/19/2012 3:40 PM EDT
If I'm reading this correctly, Intel/MU say they have started "volume production" of a ferroelectric NAND device; that others (such as a group from AIST, see below) have been working on similar IP but are far behind because they are focused on (a) a different ferroelectric material as compared to the gate material Intel has developed, and (b) a more complicated FinFet structure rather the "old school" planar circuit design developed by MU.
see AIST work disclosed at:
(2008 cell demonstration)
http://www.aist.go.jp/aist_e/latest_research/2008/20080624/20080624.html
(2012 64Kb cell array demonstration)
http://www.nanowerk.com/news/newsid=23983.php
I find this all very very very difficult to believe in view of the industry's track record of premature claims of new NV memory "production;" but most of all because Intel/MU are claiming to be able to produce this planar "Fe-NAND" device at sub 30nm lithographies currently with plans to soon drop production below the 20nm node. Such devices with even half the performance claimed for the AIST cell design would go through the current FLASH application markets like something through a goose.
Has Intel/MU developed a new memory IP or just a new promotion? Have they ever submitted anything at an industry conference on such IP?
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resistion
4/19/2012 10:25 PM EDT
So far it's just floating gate with high k at 20 nm.
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cidbarca
4/20/2012 3:17 AM EDT
Thanks resistion, I think I see now. The high-k dielectric's polarization isn't used as a memory element at all.
Is it correct to think of it as simply providing a capacitance threshold that's used as the limit on current flow?
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peter.clarke
4/20/2012 6:36 AM EDT
Although, Intel did gain a lot of ferroelectric memory knowledge in their research with Thin Film Electronics a few years back.
But I agree there is no sign they are using that knowledge directly in these NAND flash memories.
The conventional wisdom is for companies to go to vertically stacked NAND memory cells thus keeping the same planar geometry (and electrons per bit) while getting greater memory denistry per die area.
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