Startup claims 'Holy Grail' of SoC design

4/23/2012 5:10 PM EDT

All you C-programmers out there unite! Now all you need to do is describe your application by a C program, plus a set of test stimulus vectors, and this startup can give you an foundry-ready SoC design in just a few weeks. Sound too good to be true? Yes it does. However, the principals have the credentials to back up the boast, and a customer list that includes a mobile LTE physical layer chip that is already on the market.

4/23/2012 5:45 PM EDT

C code in and GDSII out? So we are to believe that in addition to a front end tool that analyzes the C code and does hardware-software partitioning and architecture optimization, they also have a synthesis engine, a place & route engine and a static timing analysis engine? One tool that replaces the entire tool chain for IC design?

Something said in the article sounds suspicious: "The resultant GDSII design, from which an EDA system can produce the file that goes to TSMC..."

What "EDA system" and why? If this new tool outputs GDSII, then you're done -- unless the GDSII has DRC violations, or the underlying design has timing violations, etc. If the GDSII that is output by this tool isn't 100% ready for TSMC, they why do they bother generating it? A netlist that is ready for P&R would be a lot more useful than a GDSII file that is not quite ready for manufacturing.

4/23/2012 7:27 PM EDT

A few things.

First off, this is not being sold as a tool. You send your C-algorithm along with some specifications (see below for an excerpt from their webiste), and then you are sent back a GDSII targeted for a particular Foundary + process, 8-16 weeks later. This is more of an accelerated consulting agreement. I agree with Frank that having an RTL netlist as well would be more useful.

Second, the figure in this article makes it clear that there is a particular architecture with a customized DSP, microcontroller, and peripherals. It isn't clear what the level of customization here is. This could range from very sophisticated program analysis mixed with behavioral synthesis and HW/SW partitioning to a template architecture which is hand-tweaked for the given application.

Finally, without more information it's unclear what the real approach is and how legitimate it is without more information. All of this said, very interesting.

--- Quoting their website at: http://www.algotochip.com/about.html
The following are the required information from the customer:
C-Code for the algorithm (Fully support ANSI C and no changes required to customers C-Code)
Test-Vectors to check the C-Code
System Specification
Desired Fabrication House and Process
Desired Standard Library and Memory Compilers
Real-Time performance constraints
Target Area and Power
Testability Features (scan, bist etc)
Peripheral Description

4/23/2012 10:43 PM EDT

Thanks for your interpretation Dr Trevorkian. I didn't check their website, just read the article, and my skepticism was raised by several comments including "suite of software tools that interprets a customers' C-code without their having any knowledge of Algotochp's proprietary technology and tools."

So I interpreted it the same way you did, as a sort of consulting agreement, with the added twist of "we have some proprietary tools that we can't let customers have access to, but our guys know how to run them."

I should think a potential customer would be more comfortable if they just said they have a customizable VLIW or whatever it is, and proprietary tools to match, and that they also have in-house implementation experts and licenses for the usual IC implementation tools -- Synopsys, Cadence, Mentor, etc. -- because nobody in their right mind is going to sign off on a tapeout of some GDSII generated by a proprietary tool, with STA, DRC, LVS, power analysis & IR drop analysis, etc. also performed by a proprietary tool.

4/23/2012 10:58 PM EDT

This sounds like a mechanical turk to me. No big news.

4/24/2012 12:00 AM EDT

If they really have achieved what they claim, that is to take a C algo to GDSII in a few weeks, with comparable power/area as of traditional RTL design, then thats really awesome. However many companies have made similar claims in the past and failed pathetically in the market, which makes me a bit skeptical.

4/24/2012 10:46 AM EDT

There is another company doing the same kind of things, with a Matlab-like entry source code and a flexible signal coprocessor: www.simpulse.fr

4/24/2012 1:28 PM EDT

Time will tell if this is a successful methodology. It may only work in specific cases or it may be a real breakthrough.

4/24/2012 4:15 PM EDT

This sounds like a quick & dirty "disposable" mask data substitute for a traditional design house for those who don't have a vested interest in mask data maintenance and re-use. Unless these magical super-secret tools are eventually released into the wild, I don't see this approach getting very popular. Although it sounds impressive in theory, I think the real world will get in the way of their success. The design process is fundamentally iterative in nature, and anything designed using a linear approach is almost guaranteed to come up short.

4/24/2012 6:47 PM EDT

Having managed ASIC designs for several years I doubt whether this new design technology can replace what tens or hundreds of designers per project are currently doing...sounds too good to be true...maybe for simple designs with far from optimum implementation...but if I am wrong these guys will swallow Cadence, Synopsys and Mentor in one scoop ;-)...Kris

4/25/2012 10:24 AM EDT

Sorry left the comment in teh wrong box :)

4/26/2012 11:33 AM EDT

Looks like it would be useful for application specific designs which need to move off FPGA or existing microprocessors for volume cost reasons, however it is likely to struggle if the clock speed is high. Consider generating a given waveform on a signal - if this has to be done by an RTL designer his state machine can be coded in gates and run off a high speed clock. For a microprocessor based solution, it needs to be coded in instructions and linked to the instruction clock rate which in turn is limited by the architecture of the microprocessor and all the other instructions that need to be implemented. There may be ways around this:
1) spot all such signals and build little RTL sections for each and then have them triggered by the microprocessor instructions
2) have a separate microprocessor for each set of signals and get the clock speed to match
But then it starts looking more custom than automated. Perhaps that explains the spread in times it takes to deliver a solution.
A long time ago I used a certain company's behavioural synthesis tool to try to implement a video scaler. The reps swore blind it was up to the task, but it then transpired that although it could quite happily model what I wanted to do, it could not get the performance because the dominant delay was in the "next state" logic and that was not part of what the tool could optimise for timing. In this current case, the next state logic is exactly what the microprocessor is doing it seems, so there are likely to be similar issues.

If what you want is just a faster, cheaper and lower power version of something you already do in C then that is ok, but I am sceptical it is an alternative for what people design chips in RTL for.

4/26/2012 8:07 PM EDT

Interesting to read and learn about the process of making a SoC. Looks like 8 to 16 weeks is still a short time. I will keep an eye on the market to see if this is really a breakthrough. Though, I think like in most cases... it will work for some but not for others. We'll see.

4/28/2012 9:30 AM EDT

They take C algorithms and test vectors as input. They did not say C program.

No doubt the C algorithms have to model the RTL design, so they take a design modeled in C as input to the EDA tool.

I am doing a similar thing with C# as a hobby project and it is not hard to do BUT the designer has to do the hardware design first.

The main advantage is that a SW IDE has much better debug/incremental compile capability than the HW EDA tools. I can step through the model and make changes at a breakpoint and continue with practically no delay as opposed to recompiling HDL and whatever else the tool needs to do.

So the hook is to let people assume the input is a C program, but in reality it is another HDL of sorts that is used to generate HDL that EDA can use. The logic design is first done by generating a restricted/subset of C.

4/28/2012 8:02 PM EDT

Unless their hardware architecture is heavily constrained beforehand, I can't see this being the case.... unless they've managed to solve an NP-hard problem with today's computer technology and the rest of humanity does not know it yet :-)

5/2/2012 9:55 AM EDT

This has been debated now for 20 years. I don't see one of the primary tradeoffs discussed: per unit cost optimization (ie, die area) of this method versus current design flow. A bigger die *might* be acceptable for low cycletime, low volume products. And how many of those exist out there?

5/2/2012 10:11 AM EDT

Not too many @gatorfan...and many of those can be just implemented in FPGA

6/18/2012 2:27 AM EDT

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