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beatnik_8983
No way..graphene !! It will be silicon all the way..
resistion
2y nm DRAM without EUV, let's get over it.
Intel exec says fabless model 'collapsing'
Rick Merritt
4/24/2012 1:10 PM EDT
SAN FRANCISCO – It’s the beginning of the end for the fabless model according to Mark Bohr, the man I think of as Mr. Process Technology at Intel.
Bohr claims TSMC’s recent announcement it will serve just one flavor of 20 nm process technology is an admission of failure. The Taiwan fab giant apparently cannot make at its next major node the kind of 3-D transistors needed mitigate leakage current, Bohr said.
“Qualcomm won’t be able to use that [20 nm] process,” Bohr told me in an impromptu discussion at yesterday’s press event where Intel announced its Ivy Bridge CPUs made in its tri-gate 22 nm process. “The foundry model is collapsing,” he told me.
Of course Intel would like the world to believe that only it can create the complex semiconductor technology the world needs. Not TSMC that serves competitors like Qualcomm or GlobalFoundries that makes chips for Intel’s archrival AMD.
Intel used the Ivy Bridge event to spin the tale of how part of the secret to its success is its close partnership between process and chip designers.
Kirk Skaugen, the new general manager of Intel’s client PC group, moderated a Q&A with Bohr and Brad Heaney, the Ivy Bridge program manager. In addition to working together on Intel’s first CPUs using 3-D transistors, the two collaborated on Intel’s first processors using high-K metal gate technology.
“Being an integrated device manufacturer really helps us solve the problems dealing with devices this small and complex,” Bohr said in the Q&A.
I don’t doubt that for a minute. Since the dawn of submicron design, EE Times has been writing about the need for ever closer collaboration between chip and process designers. An Nvidia physical design exec underlined the same point in a recent talk at Mentor Graphics’ annual user group meeting.
But Bohr stretches the point too far when he says the foundries and fabless companies won’t be able to follow where Intel is going. I have heard top TSMC and GlobalFoundries R&D managers make a good case that 3-D transistors won’t be needed until the 14 nm generation. For its part, TSMC said at 20 nm there is not enough wiggle room to create significant variations for high performance versus low power processes.
I neglected to ask Bohr whether Intel has separate high performance and low power processes in its 22 nm technology. (Anyone from Intel is welcome to chime in here.)
However, in an open Q&A, Bohr said Intel has completed work on an SoC-specific version of its process technology. It plans going forward to have an SoC variant a quarter or two after each main process is complete.
For its part, Qualcomm would not provide its opinions on TSMC’s 20 nm plans. The company did say in its recent quarterly earnings call it can’t get enough 28 nm technology from TSMC to meet product demand, so it is working to develop multiple new sources it expects will come online later this year.
That’s a big opportunity for a GlobalFoundries, UMC or other fabs to step up. Given the close sharing of design details required to make 28 nm SoCs, it’s more of a risk than an opportunity for Qualcomm to work with Samsung’s foundry folks, Bohr said, given Samsung has its own Exynos mobile SoCs.
I asked Bohr to whom Intel is providing access to its 22 nm process besides two announced partners—Achronix and Netronome. He only said that Intel does not want to be in the general foundry business, but it makes its technology available to a few strategic partners.
Intel has no monopoly on smart process technology engineers and designers. But it does have some brilliant ones, and it has learned to market them smartly. Bohr and Heaney even appeared yesterday in another one of Intel’s playful videos shrinking the two engineers so they could tour the insides of an Ivy Bridge chip.
Looking ahead, Bohr said Intel has finished characterizing its next-generation 14 nm process using immersion lithography. It even has “encouraging results” suggesting it will be able to use immersion litho for the 10 nm node that is still in early planning phase.
“We think we have a [10nm] solution using immersion lithography—we’d love to have extreme ultraviolet [EUV] lithography, but we are not counting on it,” said Bohr in the event Q&A.
As a follow up, I asked whether Intel has other new process tricks like 3-D transistors at 14 and 10 nm. His answer: “Yes!”
I love it when companies celebrate and provide access to their top engineers. But I hate it when they are so well trained by their PR departments.
Skaugen (left) queries Bohr and Heaney (right) on their process/chip design collaboration.
Bohr claims TSMC’s recent announcement it will serve just one flavor of 20 nm process technology is an admission of failure. The Taiwan fab giant apparently cannot make at its next major node the kind of 3-D transistors needed mitigate leakage current, Bohr said.
“Qualcomm won’t be able to use that [20 nm] process,” Bohr told me in an impromptu discussion at yesterday’s press event where Intel announced its Ivy Bridge CPUs made in its tri-gate 22 nm process. “The foundry model is collapsing,” he told me.
Of course Intel would like the world to believe that only it can create the complex semiconductor technology the world needs. Not TSMC that serves competitors like Qualcomm or GlobalFoundries that makes chips for Intel’s archrival AMD.
Intel used the Ivy Bridge event to spin the tale of how part of the secret to its success is its close partnership between process and chip designers.
Kirk Skaugen, the new general manager of Intel’s client PC group, moderated a Q&A with Bohr and Brad Heaney, the Ivy Bridge program manager. In addition to working together on Intel’s first CPUs using 3-D transistors, the two collaborated on Intel’s first processors using high-K metal gate technology.
“Being an integrated device manufacturer really helps us solve the problems dealing with devices this small and complex,” Bohr said in the Q&A.I don’t doubt that for a minute. Since the dawn of submicron design, EE Times has been writing about the need for ever closer collaboration between chip and process designers. An Nvidia physical design exec underlined the same point in a recent talk at Mentor Graphics’ annual user group meeting.
But Bohr stretches the point too far when he says the foundries and fabless companies won’t be able to follow where Intel is going. I have heard top TSMC and GlobalFoundries R&D managers make a good case that 3-D transistors won’t be needed until the 14 nm generation. For its part, TSMC said at 20 nm there is not enough wiggle room to create significant variations for high performance versus low power processes.
I neglected to ask Bohr whether Intel has separate high performance and low power processes in its 22 nm technology. (Anyone from Intel is welcome to chime in here.)
However, in an open Q&A, Bohr said Intel has completed work on an SoC-specific version of its process technology. It plans going forward to have an SoC variant a quarter or two after each main process is complete.
For its part, Qualcomm would not provide its opinions on TSMC’s 20 nm plans. The company did say in its recent quarterly earnings call it can’t get enough 28 nm technology from TSMC to meet product demand, so it is working to develop multiple new sources it expects will come online later this year.
That’s a big opportunity for a GlobalFoundries, UMC or other fabs to step up. Given the close sharing of design details required to make 28 nm SoCs, it’s more of a risk than an opportunity for Qualcomm to work with Samsung’s foundry folks, Bohr said, given Samsung has its own Exynos mobile SoCs.
I asked Bohr to whom Intel is providing access to its 22 nm process besides two announced partners—Achronix and Netronome. He only said that Intel does not want to be in the general foundry business, but it makes its technology available to a few strategic partners.
Intel has no monopoly on smart process technology engineers and designers. But it does have some brilliant ones, and it has learned to market them smartly. Bohr and Heaney even appeared yesterday in another one of Intel’s playful videos shrinking the two engineers so they could tour the insides of an Ivy Bridge chip.
Looking ahead, Bohr said Intel has finished characterizing its next-generation 14 nm process using immersion lithography. It even has “encouraging results” suggesting it will be able to use immersion litho for the 10 nm node that is still in early planning phase.
“We think we have a [10nm] solution using immersion lithography—we’d love to have extreme ultraviolet [EUV] lithography, but we are not counting on it,” said Bohr in the event Q&A.
As a follow up, I asked whether Intel has other new process tricks like 3-D transistors at 14 and 10 nm. His answer: “Yes!”
I love it when companies celebrate and provide access to their top engineers. But I hate it when they are so well trained by their PR departments.
Skaugen (left) queries Bohr and Heaney (right) on their process/chip design collaboration.
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rick.merritt
4/24/2012 2:45 PM EDT
Is Bohr right, or just chucking FUD at competitors?
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chipmonk
4/24/2012 2:53 PM EDT
Let me repeat myself : the free ride that the "fabless wonders" and offshore foundries have been enjoying at the expense of serious IDMs is coming to a close. IBM is discredited after they misled hanger-on foundries into the HKMG fiasco. They can no longer play the spoiler even with SOI ( to lower leakage ).
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BicycleBill
4/24/2012 2:57 PM EDT
IMO, the reality is that one size/type of solution does not work right for all players. Fabless is great for some design houses, markets, and products, but not a good fit for others. Whenever we try to posit that one approach is "right" or "best", we are ignoring the engineering reality: it is all about managing and balancing tradeoffs and priorities, given your available resources and objectives.
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MikeSmith2011
4/24/2012 3:07 PM EDT
Could we be reaching the end of Moores law and technology shrinks in silicon manufacturing. Tri-gate might have mitigated the issues at the 32-22nm migration step but the fact that Intel had to resort to such a radical step is worriesome. What after that? 14nm? 10nm? Will tri-gate survive the shrinks?
If this is the end of the shrink race then this spells bigger trouble for Intel than the fabless makers. In order to keep the lead in process technology they will have to make radical changes to their manufacturing (read more complex lower yields, higher costs) and if they stumble or stop, guess what? All the minions of semi players will have a level playing field. Then it will be about who has the best design.
Oh my!
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yalanand
5/4/2012 1:43 AM EDT
@MikeSmith2011, what after 14nm,10nm I think after this we will graphene transistor era.
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beatnik_8983
7/11/2012 1:32 AM EDT
No way..graphene !! It will be silicon all the way..
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the_floating_ gate
4/24/2012 6:03 PM EDT
IDM versus foundry:
When asked if the multipatterning issues at 14-nm applied to both integrated device manufacturers (IDMs) and foundries Meurice said: "At 14-nm foundries have a challenge that the IDMs would not have. The challenge is that thay have to deliver design rules which are less restrictive and they have to deliver a shrink that is very aggressive." As such the decision to go to EUV for 14-nm concerns the foundry environment more than the microprocessor environment, Meurice said.
http://www.eetimes.com/electronics-news/4371327/DRAM-foundry-logic-EUV-lithography-ASML
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resistion
7/2/2012 11:25 AM EDT
2y nm DRAM without EUV, let's get over it.
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me
4/24/2012 8:12 PM EDT
Some companies can innovate internally, like Intel. Others cannot, even though they are big. A number of years ago, all jump on the band wagon to trash the ecosystem. Now that destruction is nearly complete. Those who cannot innovate internally may enjoy a hard earned collapse.
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resistion
4/24/2012 9:59 PM EDT
The foundry model is not affected by the technology status so much as the current business situation. It may help the foundries to consider IDM-type projects, just as IDMs are considering foundry-type projects.
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Neo1
4/24/2012 10:28 PM EDT
This is all hokum, and lot of smoke with no real fire. True Fabless won't work for all but the fact is it works for most and anyone thinking he can go from fabless to churning off sub 32nm wafers is probably out of his mind. Fab cost work to everyones advantage when its billions of dollars are amortized across billions of wafers.
Intel also would have gone fabless if they were not running a monopoly in PC business.
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me
4/25/2012 12:01 AM EDT
Now they have a chance to be the monopoly in the foundry business. But I doubt they can capitalize on it. It has been a half trick pony for the time immemorial.
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KB3001
4/28/2012 7:05 AM EDT
Absolutely, what Mr Bohr is saying here is pure chauvisnism IMO. Instead of predicting the demise of the fabless/foundry model, he should have simply predicted much closer tie-up between fabless companies and foundries in the future e.g. through joint ventures.
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chanj
4/25/2012 1:14 AM EDT
A fabrication facility is costly to build. Foundry business and fabless will continue exist and work together to bring various components to the market.
Nonetheless, if design and production can work closely together like Intel, the company would have better competitive edge. The reason that Intel still push x86 based CPU into mobile market is they believe they can produce a low power consumption CPU using product technology. Let's imagine if Intel started producing its own ARM.
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resistion
4/25/2012 1:20 AM EDT
Bohr's statements apply to the bleeding edge of 20 nm and below. Intel doesn't have any trailing edge fabs (like 0.18 um and older). It has one 200 mm fab in Hudson at 130 nm.
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agk
4/25/2012 4:36 AM EDT
Golden words "part of the secret to its success is its close partnership between process and chip designers" and Intel is leading.They have the power full R&D team with sufficient finance.
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wilber_xbox
4/25/2012 2:35 PM EDT
given the fact that not many companies can develop technologies at 2X and 1X nodes due to high monetary cost, going solo is not an option. Either collaboration or going fabless is an option. Intel is surely ahead by 2 to 3 years as far as technology is concerned.
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cdhmanning
4/30/2012 7:56 PM EDT
If you take a fat unfit person (like me) and tie the latest carbon fibre running shoes on my feet it won't help. An athlete with boots on will still run faster.
The same goes for CPUs.
Intel might be ahead in process, but that does not give them a lead overall because their architecture is so terrible.
ARM stuff is still better for most applications even when built on older (and thus cheaper) fab technologies.
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Vancouver
4/25/2012 5:36 PM EDT
Intel Corporation is a Patriot while most other fabless are pinheads.
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cdhmanning
4/30/2012 7:50 PM EDT
If you're such a flag-waver, insist that your next cell phone runs an Intel CPU.
Let us know how you get on carrying a car battery for power.
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Simon7382
4/30/2012 11:54 PM EDT
Well, no flag waving but I would not dot count Intel out in the low power/cell phone processor game. They are usually not the first (same as Msoft) but when they come they mow down the competition. This will be especially true if in fact TSMC will have a serious hick-up below 20nm, which may well happen.
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Simon7382
4/30/2012 11:51 PM EDT
Pinheads, the way that idiot O'Reily on Faux Noise uses the word?? PLLLease!
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Mike Santarini
4/25/2012 6:06 PM EDT
Problem: "I hate it when they are so well trained by their PR departments."
Reporter 101 solution: Booze
Nice Piece, Amigo.
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rick.merritt
4/27/2012 1:19 AM EDT
Speaking of booze, let's grab a beer sometime ;-)
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BobsUrUncle
4/25/2012 6:09 PM EDT
Intel is basically telling Wall Street (thru the conference) AMD, Qualcomm and the rest of the industry can't compete because they're fabless and dependent on inferior technology so we deserve a better stock valuation. Ho humm. Haven't we heard this basically at every technology node?
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PV-Geek
4/25/2012 10:29 PM EDT
Intel is making fun of TSMC for limiting the process variants, but the they could stand to look in the mirror. They pretty much fill their fabs with a single product variant. I agree that very advanced products on very advanced processes will probably have to be co-developed for each other. This will cause challenges for some companies, but not most. Most foundry customers run a variety of products in smaller run rates and with more process variants. They could not ammortize the cost of doing it themselves and need a foundry model. I wouldn't be surprised to see one or two companies head back the other way or engage in a JDP model with a foundry.
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andyzg
4/26/2012 4:37 AM EDT
bohr's view is narrow in the sense that he assumes high quantity products. however, once the scaling ends slowly, the design matters more, and increasingly differentiated designs are used for different applications. NRE will matter a lot.
bohr should be worried about having only one customer.
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KB3001
4/28/2012 7:10 AM EDT
Correct. Beyond CPU, Intel does not have much scale advantage and they should (and are) very worried indeed. This bravado from Mr Bohr et al. is not fooling us....
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Simon7382
4/30/2012 11:59 PM EDT
Watch Intel taking significant share in the base-band business in a year or two using its process technology advantage. As far as "fooling us" I would much more put my money on Intel than Global Foundries or AMD or most others in the digital IC business (Qualcomm being the only possible exception).
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andyzg
5/1/2012 11:52 AM EDT
yes, well possible. nonethless, as a technology matures, the game changes from "being able to make at all" to "being able to make it economically at increasingly lower quantities" -- to satisfy increasingly diverse markets. intel should buy xilinx, add e-beam capability to their fabs, and offer a foundry model to a broad customer base that covers the whole spectrum of quantities.
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selinz
4/27/2012 11:58 AM EDT
I'm surpised to see such grandiose claims from an Intel spokesman. They have a huge talented work force and history doesn't validate a previous commenter's claim that they don't innovate. As long as your factories are running and you've got high margin products, no need to dump capacity to others and enable your competitors.
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Diogenes53
4/28/2012 2:55 PM EDT
The fabless model will continue to function but not at the leading edge. As EUV/X-ray continues to be endlessly strung out, stretching optical will require ever more magical DFM (remember DFM?) tricks and spaceless links between design and manufacturing. The foundries will cling to their guns, bibles and recipes, while fabless designers will be forced to innovate with sub-leading edge processes.
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wilber_xbox
4/28/2012 11:57 PM EDT
truly said that innovation is the key here in lithography now. without EUV, industry is still enabling 22nm, 14nm and below.
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Simon7382
5/1/2012 12:01 AM EDT
That will work for analog and mixed signal stuff, but for serious digital you need to be on the leading edge (or pretty close to it) of processing to compete.
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Or_Bach
4/29/2012 12:18 AM EDT
It would seems that Mark statement should be taken far more seriously !Lets recall the recent NVIDIA bashing of TSMC - see my recent blog: "Is NVIDIA in a Panic? If so, what about AMD? Other fabless companies?"
"http://www.monolithic3d.com/2/post/2012/04/is-nvidia-in-a-panic-if-so-what-about-amd-other-fabless-companies.html
Clearly Intel have significant advantage these days by being able to control the design, the EDA and Libraries and the fab.For the fabless module to work the largest fabless companies need to establish partnership with the EDA/Libraries provider and the foundry.But this will be very hard to do.
Alternatively they can change the game (to monolithic 3D IC ;-)
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Dave.Dykstra
4/29/2012 12:36 AM EDT
Very interesting, but over the years the number of times we see one company thinking they have a large headstart over others is legion and even more so the number of times they find that the others can come up with other ways to do the same thing. One of the most interesting was something many may remember called "micro-channel" back in the 90's. Everybody else just came up with another way to accomplish the same thing. I suspect we'll see the same here.
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maclag
4/29/2012 9:05 PM EDT
Let's not be naive: of course Intel won't praise the fabless model!
Everybody claim to have the best approach, and it's no surprise that other foundries claim 3D is not required before 14nm (going further: "you see? Intel is wasting so much money just to show off and try to justify their IDM approach!")
I'll be convinced about all of that when I'll see Intel's procs outperforming all their competitors.
Beside, if I was Intel, I'd be more careful about these claims, because we don't know how long they'll be able to compete alone in the Moore's law race...
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chipmonk
4/30/2012 12:33 PM EDT
At the launch of Ivy Bridge ( 22 nm finFET ) last week the offical Intel claim was 20 % higher performance for 20 % lower power. Would that be good enough to scare established Fabless providers of SoCs for Mobiles to abandon their generic ARM based design / Foundry / high mark - up model and switch to X86 ? Is Intel prepared to also offer some price cuts to get a design win into SmartPhone / Tablets?
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chipmonk
4/30/2012 12:39 PM EDT
(cont'd )
compared to the 35 nm node, the die size at 22 nm could be 30 % smaller and cheaper ( since they were also claiming that their finFET process costs only 2 % more than planar CMOS ).
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gatorfan
5/2/2012 10:03 AM EDT
For Bohr's comment to be credible, it needs to have a discussion of alternatives. I get the point about collaboration between design and process. But that is to imply that Qualcomm and TSMC don't collaborate similarly which would be lunacy. Qualitatively can Intel collaborate more efficiently vs Qualcomm/TSMC might be a case to make. Otherwise, what is the argument since the Semi world will not all suddenly revert to an IDM business model. It took 20 years to get where we are today. If the strategic challenges are that severe it will take another 20 years to revert. In the mean time there is a TON of demand to make the current Fabless/Foundry model "work". So, the comparison is not Intel vs Qualcomm but perhaps a near in competitor now Fabless model Intel vs AMD.
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