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vmsajja1
Altera developed a 4 chip MCM in the 90's with very little success due to ...
Steve Gabriel
We continue to enhance our Quartus II software to simplify the development of ...
3-D FPGAs enable silicon convergence
R Colin Johnson
4/24/2012 2:45 PM EDT
PORTLAND, Ore.—The three-dimensional (3-D) field-programmable gate array (FPGA) is enabling the era of silicon convergence, according to Altera Corp. (San Jose, Calif.), which is incorporating application specific integrated circuits (ASICs), application-specific standard products (ASSPs), digital signal processors (DSPs) and micro-processor units (MPUs).
"3-D affords the capability of integrating FPGAs with ASICs, with memory with ASSPs, DSPs, MPUs or even with FPGAs from other vendors, thereby boosting system performance by minimizing power, downsizing form factor and lowering BoM [bill of materials]," said Jeff Waters, senior vice president and general manager of military, industrial and computing division at Altera. "The promise of 3-D packaging is so great that Altera is dedicated to surmounting the engineering challenges of silicon interposer fabrication, optimizing resulting signal integrity, solving system integration issues, and managing yield and cost."
Altera is cooperating with TSMC to use wafer scale integration of heterogeneous chip sets with its silicon interposer which can interconnect any number or separate die inside a common package. As a result, ASICs are losing their traditional advantage in high-volume applications, according to Altera.
Traditionally, ASIC had the advantage in both chip size and cost, but at advanced processor nodes now the up-front costs for masks is $10 million and up. In fact, between 2006 and 2008, according to Waters, a three-to-one gap opened between the cost of using an ASIC and using a FPGA, with the tipping point toward FPGA, occurring circa 2009.
"Now FPGA-based designs are outgrowing ASIC-designs by 2X, because it is just too expensive to develop an ASIC except in very high-volume consumer applications," said Waters. "FPGAs are also starting to take over DSP and ASSP applications."
Today, processors with on-chip DSPs have the advantage over ASICs in every dimension except power efficiency. But Water claims that by adding heterogenous processor cores, DSPs, ASSPs and even small ASICs alongside them on same chip, FPGAs are filling the power efficiency advantage of ASICs.
"We call this silicon convergence, because by adding hardware processor cores and DSPs right on the FPGA, as well ASICs and ASSPs, these heterogeneous FPGAs are beating ASICs in all dimensions," said Waters.
For the future, the key challenge to FPGA silicon convergence is software, according to Waters. The programming problem of integrated software approach to mixed-system FPGAs with processor, DSP, ASIC ASSP all on the same chip require new programming environments that can reach all these heterogeneous blocks.
The applications of heterogenous cores are myriad. FPGAs are, for example, being used inside servers as accelerators performing the tasks of a codec, filtering, and other co-processing that boosts performance while cutting power and bill-of-materials over adding more adding more general-purpose processors to a server or graphic processor units which consume up to 10-times as much power as FPGA.
According to Waters, future demands of "Big Data" is driving FPGA use to perform unstructured data analytics, to remove latency from SSDs, to analyze video, and to perform on-the-fly encode/decode tasks that used to have to be performed off-line before data transmission.
"3-D affords the capability of integrating FPGAs with ASICs, with memory with ASSPs, DSPs, MPUs or even with FPGAs from other vendors, thereby boosting system performance by minimizing power, downsizing form factor and lowering BoM [bill of materials]," said Jeff Waters, senior vice president and general manager of military, industrial and computing division at Altera. "The promise of 3-D packaging is so great that Altera is dedicated to surmounting the engineering challenges of silicon interposer fabrication, optimizing resulting signal integrity, solving system integration issues, and managing yield and cost."
Altera is cooperating with TSMC to use wafer scale integration of heterogeneous chip sets with its silicon interposer which can interconnect any number or separate die inside a common package. As a result, ASICs are losing their traditional advantage in high-volume applications, according to Altera.
Traditionally, ASIC had the advantage in both chip size and cost, but at advanced processor nodes now the up-front costs for masks is $10 million and up. In fact, between 2006 and 2008, according to Waters, a three-to-one gap opened between the cost of using an ASIC and using a FPGA, with the tipping point toward FPGA, occurring circa 2009.
"Now FPGA-based designs are outgrowing ASIC-designs by 2X, because it is just too expensive to develop an ASIC except in very high-volume consumer applications," said Waters. "FPGAs are also starting to take over DSP and ASSP applications."
Today, processors with on-chip DSPs have the advantage over ASICs in every dimension except power efficiency. But Water claims that by adding heterogenous processor cores, DSPs, ASSPs and even small ASICs alongside them on same chip, FPGAs are filling the power efficiency advantage of ASICs.
"We call this silicon convergence, because by adding hardware processor cores and DSPs right on the FPGA, as well ASICs and ASSPs, these heterogeneous FPGAs are beating ASICs in all dimensions," said Waters.
For the future, the key challenge to FPGA silicon convergence is software, according to Waters. The programming problem of integrated software approach to mixed-system FPGAs with processor, DSP, ASIC ASSP all on the same chip require new programming environments that can reach all these heterogeneous blocks.
The applications of heterogenous cores are myriad. FPGAs are, for example, being used inside servers as accelerators performing the tasks of a codec, filtering, and other co-processing that boosts performance while cutting power and bill-of-materials over adding more adding more general-purpose processors to a server or graphic processor units which consume up to 10-times as much power as FPGA.
According to Waters, future demands of "Big Data" is driving FPGA use to perform unstructured data analytics, to remove latency from SSDs, to analyze video, and to perform on-the-fly encode/decode tasks that used to have to be performed off-line before data transmission.
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sharps_eng
4/24/2012 3:16 PM EDT
I don't suppose it would be a cost-effective use of all that 3D space to incorporate the necessary decoupling capacitors?
The amount of real estate given to external capacitors 'just in case' is insane; the chip makers know how much capacitance it needs, so fit it insid and let the rest of us use the PCB for something that us actually useful to our app.
Yes, I know, if we are pumping the I/O at LF we may need extra caps, credit us with _some_ design skills; what we don't have is PCB space, or indeed the extra layers needed to track past the decoupler arrays.
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R_Colin_Johnson
4/24/2012 7:13 PM EDT
Yes, that is possible, but the size of the bypass capacitor is often application dependent, as you mentioned. Xilinx for instance has publically state that they may add bypass caps to their silicon interposer.
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R_Colin_Johnson
4/24/2012 6:53 PM EDT
Altera has already started adding MPUs, DSPs, ASICs, ASSPs to its FPGAs making silicon convergence a fait accompli, but Waters point here is that with silicon interposers this ability now has a 3-D platform to take it mainstream.
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Sanjib.Acharya
4/29/2012 4:23 AM EDT
How about the development tools? Is Altera planning to come out with a new development tool set as "Vivado Design Suite" of Xilinx to make the development easier for the 3D platform?
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KB3001
4/29/2012 5:32 AM EDT
Software remains the big problem as the article rightly points out...
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Steve Gabriel
5/7/2012 12:54 PM EDT
We continue to enhance our Quartus II software to simplify the development of our devices, which includes enhancements that enable the development of 2.5D devices (integrating multiple FPGA die in a package leveraging an interposer). Due to the large number of challenges at all levels of multi-die design, silicon vendors and EDA vendors alike will need to work closely together to develop the next generation of EDA tools.
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vmsajja1
5/8/2012 10:59 AM EDT
Altera developed a 4 chip MCM in the 90's with very little success due to availability of tools to wring out efficiencies in the design. It is likely the same problems will be seen with this new package.
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