GlobalFoundries installs gear for 20-nm TSVs

SAN JOSE – GlobalFoundries is installing equipment to make through-silicon vias in its Fab 8 in New York. If all goes well, the company hopes to take production orders in the second half of 2013 for 3-D chip stacks using 20 and 28 nm process technology.

GlobalFoundries is working with multiple packaging companies including Amkor to develop process flows to create stacks with through-silicon vias (TSVs). The foundry’s archrival, Taiwan Semiconductor Manufacturing Co., announced late last year it will go it alone, handling all steps in the 3-D stacking process in a move TSMC said will reduce costs and risks of shipping the thin wafers the technique requires.

“Our customers have asked us for an alternative path,” said Dave McCann, senior director of packaging R&D for GlobalFoundries.

“They don’t want to have all their business controlled at one spot--they like the transparency in yields, pricing and choice,” said McCann who left Amkor a year ago to join the foundry. “Bringing it all in house negates the expertise of the packaging companies, and we need to access their experts,” he said.

Some chip designers want to define their own supply chain for 3-D chip stacks, others will let GlobalFoundries set up the supply chain, McCann said.

“There won’t be just one supply chain,” he said. “Our model is more difficult to bring up in the beginning, but we think it will result in the best long term solution for the industry,” he added.

The news is the latest milestone in the industry’s move toward joining multiple die in a single package using vertical TSV copper interconnects. The approach is expected to bolster chip performance by dramatically increasing the speed and bandwidth of links between logic and memory chips.

GlobalFoundries is spending “tens of millions” on a tool suite. It includes unspecified suppliers of systems to add a thick photo resist to find TSV locations and etch the vias, as well as systems to deposit an oxide layer into the holes, put in barrier and seed layers for copper and handle CMP planarization.

The systems should be in place and qualified by the end of July, with about half of them installed today, McCann said. The company aims to run its first 20 nm test wafers with TSVs in October and have data on packaged chips from its partners by the end of the year.

GlobalFoundries’ schedule calls for having reliability data in hand early next year. The data will be used to update the company’s process design kits so its customers can start their qualification tests in the first half of the year.

If all goes well, first commercial product runs of 20 and 28 nm wafers with TSVs can start in the second half of 2013 and ramp into full production in 2014, McCann said.

Among the challenges ahead, the fab and packaging companies need common metrology tools and processes to make sure TSVs are of a uniform depth and fill level. GlobalFoundries will make 55-micon deep TSVs in thick wafers it ships to packaging companies that will thin the wafers, then do back-side metallization, McCann said.

Plating speed and design for test techniques may determine yields, and thus costs of the technique, McCann said. EDA companies are developing tools to control placement of blocks so vertical connections between logic die can be optimized in future designs, he said.

If there is enough demand for TSVs, GlobalFoundries also will bring up the technology in its Fab 1 in Dresden. A fab in Singapore will be used for additional capacity for 2.5-D chips using silicon interposers if demand for the process exceeds what the New York fab can handle. GlobalFoundries is also exploring use of TSVs for MEMS and other products.

So far, three types of chip designs want to use TSVs. High-end mobile application processors will use TSVs to link to memories, high-end graphics and CPUs with use it to link to DRAMs and memory stacks that may or may not include any logic also will use TSVs, McCann said. All three classes could be in production in 2014, he said.

Network processors may take a half step forward, using silicon interposers to link processors and memory die laid side-by-side.  “The network processors generate too much heat for the junction temperature maximums for the DRAMs,” said McCann.

The Common Platform group that includes GlobalFoundries, IBM and Samsung has so far not collaborated on defining a 3-D chip stack process. The group’s focus to date has been on process technologies, not packaging issues.

GlobalFoundries recently announced it has shipped a quarter million wafers using high-K metal gate technology used for its 32 and 28 nm processes. Its 20 nm process also will be based on HKMG technology. GlobalFoundries said it will not use 3-D transistors, also known as FinFETs, until its 14nm generation.

Image courtesy of Royal Institute of Technology (KTH Stockholm).