Moore’s Law more slowly
The good news is experts see no fundamental barriers to scaling process technology down to at least 7 nm. The bad news is “as you go to smaller nodes the benefits of scaling are being eroded significantly,” said Iyer of IBM.
The culprit is the lack of any new lithography techniques. Today’s 193 nm immersion lithography systems are being asked to create 22 and even 14 nm features.
“This does not come free, the costs are becoming formidable,” Iyer said. “Complex patterning solutions are the cause of the angst we are having,” he added.
Indeed costs of lithography will jump significantly at 20 nm and soar at 14 nm, said Kengeri of GlobalFoundries. The additional complexities and process and design costs are among the reasons the traditional two-year cadence between nodes is lengthening, he said.
It took three extra quarters for the industry to qualify the 32/28 nm node and the ramp for the technology was a quarter longer than usual, Kengeri said. “Things are slowing down,” he added.
According to a Merrill Lynch report, the cost of a single SoC project could bloat to $250 million at the 14 nm node, said Roawen Chen, vice president of manufacturing at Marvell Semiconductor. Masks costs alone will be about $7 million and the time from tapeout to first silicon could expand to six months, he said.
“The bottom line is its becoming very expensive,” Chen said.
The good news is one IBM researcher showed ways to make devices with as few as 25 atoms, opening the door to a 7 nm, process node. “Until we get to 7 nm or so there are no fundamental issues we see,” said Iyer.