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MarineDir
While scaling down exponentially to smaller and smaller sizes is the goal for ...
Adele.Hars
Rick, if you or anyone else wants to better understand fully depleted (FD) ...
Chip execs see 20 nm variants, 3-D ICs ahead
Rick Merritt
4/27/2012 12:43 AM EDT
Moore’s Law more slowly
The good news is experts see no fundamental barriers to scaling process technology down to at least 7 nm. The bad news is “as you go to smaller nodes the benefits of scaling are being eroded significantly,” said Iyer of IBM.
The culprit is the lack of any new lithography techniques. Today’s 193 nm immersion lithography systems are being asked to create 22 and even 14 nm features.
“This does not come free, the costs are becoming formidable,” Iyer said. “Complex patterning solutions are the cause of the angst we are having,” he added.
Indeed costs of lithography will jump significantly at 20 nm and soar at 14 nm, said Kengeri of GlobalFoundries. The additional complexities and process and design costs are among the reasons the traditional two-year cadence between nodes is lengthening, he said.
It took three extra quarters for the industry to qualify the 32/28 nm node and the ramp for the technology was a quarter longer than usual, Kengeri said. “Things are slowing down,” he added.
According to a Merrill Lynch report, the cost of a single SoC project could bloat to $250 million at the 14 nm node, said Roawen Chen, vice president of manufacturing at Marvell Semiconductor. Masks costs alone will be about $7 million and the time from tapeout to first silicon could expand to six months, he said.
“The bottom line is its becoming very expensive,” Chen said.
The good news is one IBM researcher showed ways to make devices with as few as 25 atoms, opening the door to a 7 nm, process node. “Until we get to 7 nm or so there are no fundamental issues we see,” said Iyer.
The good news is experts see no fundamental barriers to scaling process technology down to at least 7 nm. The bad news is “as you go to smaller nodes the benefits of scaling are being eroded significantly,” said Iyer of IBM.
The culprit is the lack of any new lithography techniques. Today’s 193 nm immersion lithography systems are being asked to create 22 and even 14 nm features.
“This does not come free, the costs are becoming formidable,” Iyer said. “Complex patterning solutions are the cause of the angst we are having,” he added.
Indeed costs of lithography will jump significantly at 20 nm and soar at 14 nm, said Kengeri of GlobalFoundries. The additional complexities and process and design costs are among the reasons the traditional two-year cadence between nodes is lengthening, he said.It took three extra quarters for the industry to qualify the 32/28 nm node and the ramp for the technology was a quarter longer than usual, Kengeri said. “Things are slowing down,” he added.
According to a Merrill Lynch report, the cost of a single SoC project could bloat to $250 million at the 14 nm node, said Roawen Chen, vice president of manufacturing at Marvell Semiconductor. Masks costs alone will be about $7 million and the time from tapeout to first silicon could expand to six months, he said.
“The bottom line is its becoming very expensive,” Chen said.
The good news is one IBM researcher showed ways to make devices with as few as 25 atoms, opening the door to a 7 nm, process node. “Until we get to 7 nm or so there are no fundamental issues we see,” said Iyer.
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Adele.Hars
4/27/2012 10:44 AM EDT
Rick, I don't get it. At the GSA Summit, you've got the big guns of SOI making major presentations -- about a quarter all told of the presentations included SOI, but no mention of anything SOI in your article? You have IBM SOI/eDRAM guru Subu Iyer -- he must have mentioned that they're doing their FinFETs on SOI, no? And then you had ST's Joël Hartman Keynote Address: The Case for SOI Technology. And Chenming Hu certainly talked about it in his keynote. And Soitec's Paul Boudre was in on the panel discussion. Are you maybe planning a follow-up?
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chrmjenkins
4/27/2012 11:37 AM EDT
I would think SOI is a given in many places. Leakage starts to dominate power at feature sizes that small.
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rick.merritt
4/27/2012 1:25 PM EDT
Frankly, yes the event was something of an SOI love fest. But it's a topic that has been around for years and one I (also frankly) don't have much perspective on.
So I focused on what seemed like the top issues I understand and are significant to a broad readership: The industry is moving to 3-D ICs, there is a debate about 20nm and the outlook for CMOS is hard but OK to 7 nm.
I'll let those interested in marketing SOI take out ads ;-)
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CamilleK
4/27/2012 6:06 PM EDT
I agree. I think this or a separate article needs to present the SOI portions of this GSA Silicon Summit. I did learn a lot about the merits of FD-SOI specially at low voltages. Items like ST is using this technology for 28 and 20nm were relevant. The numbers were actually impressive.
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rick.merritt
4/29/2012 7:16 PM EDT
I do not have any notes on the SOI portions of the event, but I welcome anyone to submit a guest opinion article summarizing what they learned...or just post a few factoids here.
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Adele.Hars
5/2/2012 9:37 AM EDT
Rick, if you or anyone else wants to better understand fully depleted (FD) planar or FinFET (3D) SOI (all very different from the partially depleted SOI IBM et al have long been using for high perf), lots of good info at www.soiconsortium.org. Also recommend an excellent white paper there posted by ST explaining their choice of FD-SOI for 28nm SOCs.
And ST-Ericsson's got a really interesting blog going on about it it (they tape out the new NovaThor smartphone SOC on 28nm FD-SOI in Q3) -- see http://blog.stericsson.com/blog/2012/04/st-ericsson-general/fd-soi-a-process-booster-for-st-ericssons-next-generation-novathor-part-1/ . He says that FD-SOI at nominal voltages gives similar peak performance to HP processes and more than 35% performance improvement compared to LP at same Vdd; and it does far better on leakage & variability.
But I too would really like to hear more from anyone who was at the GSA Summit.
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docdivakar
4/30/2012 5:27 PM EDT
@CamilleK: you should take up on Rick's suggestion and write on the SOI portion of the GSA Summit last week... I missed out much of the morning due to prior commitments.
MP Divakar
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rick.merritt
4/29/2012 7:18 PM EDT
Adele: As noted below, if you or others have insights on SOI from the GSA event feel free to submit a guest opinion article to me or our Web editor Dylan McGrath--or post a few brief insights here.
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wilber_xbox
4/27/2012 11:33 AM EDT
plenty of good stuff already in this article. 3D stack, integration and devices are coming and its exciting to be the least.
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Dave.Dykstra
4/29/2012 12:26 AM EDT
Well, in any event, it is interesting to see where the industry may be going with 20-nm and 3-D and what they are currently thinking.
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docdivakar
4/30/2012 5:24 PM EDT
@rick.merritt: looks like you left before the GSA 3DIC Workgroup meeting that day where some interesting points were made (couple from myself!). While it is true that some companies (Samsung, Micron) are building 3DIC (TSV-enabled) memory products, the ecosystem challenge still remains as are the standards. There will be more discussions on these two at the upcoming GSA meetings.
MP Divakar
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MarineDir
6/19/2012 10:55 PM EDT
While scaling down exponentially to smaller and smaller sizes is the goal for engineers, if it makes no financial sense to do so, businesses would not fund that kind of development. Innovation here depends a lot on the profitability of making smaller and smaller chips. No one would want to spend so much resources to make a smaller chip if it doesn't have potential to make more money for chip makers.
Mary - http://www.jensenmarinedirect.com
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