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resistion
At VLSI, it was revealed the fins had 30 nm half pitch. So Intel has entered ...
peter.clarke
The original explanation from Intel, why back when, was that the gate wrapped ...
Intel's FinFETs are less fin and more triangle
Peter Clarke
5/17/2012 7:39 AM EDT
LONDON – Reverse engineering and analysis consultancy Chipworks Inc. has posted microscope cross-sections of parts of the 22-nm Ivy Bridge processor from Intel that has revealed that the FinFETs, which Intel calls tri-gate transistors, are in fact trapezoidal, almost triangular, in cross-section.
The ICs were 64-bit, four-core Xeon E3-1230 CPUs intended for the server market, which Chipworks (Ottawa, Ontario) said it obtained in Hong Kong, China.
The triangular section is markedly different to the idealized rectangular section that Intel had shown previously in 2011. However, it is not clear whether the non-vertical sides to the fins are a non-critical manufacturing artifact or are deliberately engineered by Intel and have a critical impact on electron mobility or yield.
Gold Standard Simulations Ltd. (Glasgow, Scotland), a spin-off from the University of Glasgow led by Professor Ase Asenov as CEO, responded by saying on its website: "There is a lot of speculation about the possible advantages and disadvantages of the trapezoidal, or almost triangular, shaped 'bulk' FinFET." GSS has performed a simulation analysis of the FinFET using its statistical 3-D TCAD simulator called Garand.
Comparison of the TEM image of one of the FinFETs from Fig. 6 of the Chipworks blog (above) with the Garand simulation domain of Gold Standard Simulations.
GSS's simulation was used to explore the dependence of threshold voltage on gate length for the trapezoidal Intel transistor and an equivalent rectangular-fin transistor. "Clearly the rectangular fin has better short channel effects. Still, the million-dollar question is if the almost-triangular shape is on-purpose design, or is this what bulk FinFET technology can achieve in terms of the fin etching?"
The comparisons between dimensionally comparable rectangular and trapezoidal FinFETs are not markedly different but as GSS had no knowledge of doping profiles it assumed a lightly doped channel. At the same time GSS acknowledged that there is a high doping concentration stopper below the fin in the shallow trench isolation (STI) region. "Clearly FinFETs are more complicated devices in terms of understanding and visualization compared to the old bulk MOSFETs," GSS concluded.
Related links and articles:
Dick James' blog at Chipworks
GSS' discussion of trapezoidal FinFET
News articles:
Analysts start Intel Ivy Bridge CPU teardown
Chipworks tears down Samsung PCM phone
Startup offers 'variability' modeling service
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any1
5/17/2012 12:20 PM EDT
I suspect that the "triangle" shape represents some compromise between what is simple and reproducible to fabricate with regards to high volume manufacturing considerations, and what is the ideal shape from from an electrical standpoint. It is also a more mechanically robust shape for a relatively high aspect ratio structure (less likely to break due to vibration, etc.).
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iniewski
5/17/2012 12:23 PM EDT
Avoiding sharp corners is always a good idea in silicon manufacturing due to electric field crowding in device operation...and even if you wanted sharp fin it would be difficult to make it always equally sharp hence yeild hit...I suspect 2012 pics were of the marketing types...Kris
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HowardHDC
5/17/2012 1:36 PM EDT
Simplest way to put it, rectangles have one more corner than triangles. Besides process variation, corners tend to have leakage current affecting off-stage performance, such as Vt and Ioff. In addition, the equivalent width of the FinFET may be easier to scale and control in triangular shape than in rectangular shape. It will be interesting to see NMOS vs PMOS with various width and how the width scaling is done.
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motti2
5/17/2012 2:33 PM EDT
iniewski has it right on one aspect.
Avoiding sharp corners is plausible advantage.
The second aspect I suspect is the ability to measure sidewall roughness without sidewall afm - atomic force microscopy that taps laterally ( the old IBM AFM that was a poor machine ). Here with sloped sidewalls, a topview high resolution SEM electron microscope images sidewalls usefully, and a comventional AFM topview tapping more trivially gets the needed "sidewall" roughness quantitaitvely measured with little difficulty versus the challenging vertical 90deg sidewall. And manufacturing metrology ease and accuracy of roughness here, which is a critical device parameter, since the surface is ETCHED ( worst thing you normally might do for a desired atomically smooth surface )...
Hence I suspect nano- metrology aspects are the driver ( this being a process engineer's perspective, not theoretical in the slightest )
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chipmonk
5/17/2012 3:21 PM EDT
Perhaps it was intentional to flood the media with sketches& even SEMs of rt. angled fins so that the pretenders and knock off artists would be misled for a while. But the important thing is that the power consumption for Ivy Bridge ( 22 nm, FinFET ) is NOT yet significantly less than Sandy Bridge to get a foot in the door at the SoC for SmartPhones house.
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I_B_GREEN
5/17/2012 3:48 PM EDT
hellooow fins are triangles!
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peter.clarke
5/18/2012 5:33 AM EDT
in elevation but not in cross-section
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PV-Geek
5/17/2012 7:08 PM EDT
Corner leakage is usually a problem, but so is reproducability and control. It is difficult to know from so little data, how much of this triangle approach is for leakage vs. process control (yield). If the power levels don't give a dividend it will all be for naught.
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resistion
5/17/2012 9:56 PM EDT
I'd always expect a round top, but the sidewall angle control affects how much footprint is actually occupied by the fin. So it's not a trivial consideration, they would have to keep the angle.
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Chipguy1
5/17/2012 11:07 PM EDT
Don't these sloped fins cause a lot of variation?
The device channel orientation is random vs 110 for ideal finfet and 100 for planar (mobility and many sources of variation)
Fin thickness depends on sidewall slope....and fin thickness sets my leakage and device threshold voltage, right?
I have bee puzzled why everyone claims trigate lowers standby leakage BUT I don't see any improvement in standby power at the chip level for intels 22nm ivy bridge??
Could this be the reasons leakage improvement does not match expectation for "ideal trigate".
http://www.anandtech.com/show/5771/the-intel-ivy-bridge-core-i7-3770k-review/20
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ChrisGar
5/18/2012 9:11 AM EDT
Finfets should provide power/perforamance advantage. Intel probably set their process to fit within a given power budget -- get as much performance as possible within that limit.
For example, lower transistor threshold voltages -- faster & more leakage. Intel would set process knobs like this to get as much performance as possible without blowing power limit.
For low power parts, Intel could set these knobs differently.
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Chipguy1
5/18/2012 11:43 AM EDT
Agree. Lower transistor threshold voltage results in faster but leaker part. If intel was taking all trigate leakage improvement and targeting performance, I don't understand why performance and or frequency is about the same? Ivy bridge frequency bins are only ~100Mhz higher vs 32nm sandy bridge. Clock frequency of 3.4 vs 3.5Ghz or performance benchmarking is less than I was expecting.
I still wonder if this trigate is really going to give intel a competitive advantage in mobile? Or is intel marketing misdirecting from their own short comings. Stock analysts in my opinion are often wrong but when I look at the data I think Gus Richards might be right.
http://www.forbes.com/sites/ycharts/2012/05/18/qualcomm-vs-intel-in-mobile-chips-somebodys-about-to-get-hurt/?partner=yahootix
Trigate has higher processing cost and extra design restriction (increases cost via larger die area). I looked at designing my I/O block with finfet (foundries name for trigate). Layout was larger (higher cost) and at block level my power was higher.
It will be interesting to watch if intel can make a better cell phone or tablet chip. But they better hurry since 28nm chips with improved power are ramping fast.
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resistion
5/18/2012 9:18 AM EDT
You'd figure with an etch mask, there should still be sharp top corners.
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motti2
5/18/2012 8:06 PM EDT
the other driver for a tapered triangular Silicon FIN is to avoid / minimize ion implant shadowing in the source drain / graded drain ion implants ( if implanted ). A vertical FIN sidewall would likely introduce asymmetric and wafer rotational dependence on Source Drain offset with respect to the edge of the FIN channel. Another process latitude driver for FIN triangular shape.... ( ie not merely metrology )
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m-Roberts
5/19/2012 1:28 PM EDT
I spoke to my go to fab guy
He said the fin shape results from a gross electrical compromise to clear spacer off fin (required for the si and SiGe fin epitaxy). Vertical fins create better electrical uniformity and performance. But its very difficult to clear spacer off a vertical fin. He does not think this fin shape will work for foundry SOC chips. Too much electrical variation and leakage
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Chipguy1
5/19/2012 3:05 PM EDT
Makes sense. Consistent with
a)
Intels 22nm chip voltage was raised to slightly greater than 1V vs foundry mobile parts that run 0.85 to 0.9V
b) intel 22nm parts having high leakage / leakage power.
I hope GSS publishes more on this topic. Very good work and helpful.
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jeremybirch
5/21/2012 4:18 AM EDT
perhaps it just explains the name "tri-gate" ie triangle gate - what else could it have stood for?
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peter.clarke
5/21/2012 10:58 AM EDT
The original explanation from Intel, why back when, was that the gate wrapped around three-sides of the rectangular cross-section fin.
If the fin is trapezoidal then tri-gate name is still ok, but if that fin is triangular in cross-section then perhaps Intel should go with bi-gate?
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resistion
6/25/2012 9:31 AM EDT
At VLSI, it was revealed the fins had 30 nm half pitch. So Intel has entered high volume double patterning, without much complaint. 14 nm should see several double patterning layers.
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