ARM CTO looks at architecture scaling for 2020 solutions

BRUSSELS – Anticipating the propagation of the Internet of things, Mike Muller, chief technology officer at ARM Ltd., discussed the needs for architecture scaling at the annual IMEC Technology Forum this week at the Square meeting center in Brussels, Belgium.

[ARM TechCon 2012, the largest ARM design ecosystem under one roof, is Oct. 30 - Nov. 1 in Santa Clara. Click here to check out agenda.]

In his keynote, Muller compared the original ARM design of 1983 to that of today’s microprocessors. Major advances have been made regarding systems, hardware, operating systems and applications but he outlined the needs of architecture scaling for 2020 solutions from tiny embedded sensors through to cloud based servers which together enable the Internet of things.

Muller provided a quick overview of the PC, from the very start when it was a hobby to when it became “the” platform for computing. “Then, we saw the beginning of the mobile dawn and mobile voice with the transition to 32-bit microcontrollers, meaning the advent of clean architecture,” he said. (See below)


Technology scaling has enabled performance improvements but in parallel power is becoming a primary constraint in the current designs, especially as we move towards an increasingly connected world.

Muller noted that operating in the sub-threshold yields large power gains at the expense of performance but he rapidly moved to Near-Threshold Computing (NTC), a design space where the supply voltage tends to equal the threshold voltage of the transistors. In contrast with sub-threshold conduction, NTC provides significant power savings without compromising on the performance.


Seeking the utmost in power reduction, Muller stated: “In the energy scavenging world, you don’t have the energy to do what you have to do. Run fast and stop is the easiest way. For aggressive power reduction, run fast and then power gate is most efficient but with a slow clock comes the need to control intra-cycle leakage. Sub-clock power gating minimizes leakage for slow clocks but you need to recalculate the logic on each new clock cycle.”

Muller then proposed the sub-clock power-gating technique for reducing leakage power in digital circuits. The technique works concurrently with voltage and frequency scaling and power reduction is achieved by power gating within the clock cycle during active mode unlike traditional power gating within the clock cycle during idle mode. ARM Cortex-M0 65nm proved 25x more energy efficient. (See below)


In 2020, Muller said, the Internet of things will represent 100 billion units, and the mobile industry has a direct impact on the hardware software value chain.

Software still uses the same 1986 technology of compilers, noted Muller. “The software is moving to frameworks and new languages -Agile, HTML5, Ruby on rails, Java, JavaScript, UML, Android. We have done compilers and have no idea what’s next. I don’t see anything approaching a revolution. I see no relevant solution except massive system reuse. We are going to have to go to the hardware world and bring software.”