If you are planning on attending DAC 2012, June 4-6, and if you’re involved in creating FPGA-based designs, then you really should bounce over to see the folks from Blue Pearl Software
(Booth #714) to see how the Blue Pearl Software Suite can improve and accelerate your FPGA design flow and IP integration.
The Blue Pearl Software Suite works with the Xilinx Vivado Design Suite running on Windows and Linux platforms. Their solution for RTL analysis includes linting, clock domain crossing (CDC), and automatic Synopsys Design Constraint (SDC) generation. With regard to these SDCs, Blue Pearl makes the synthesis and place and route phases of FPGA design implementation more efficient. The Blue Pearl Visual Verification Environment makes it easy to use for any level of FPGA designers to validate their constraints.
Furthermore, the folks from Blue Pearl say that their collaboration with Synopsys has led to an optimized flow that works with Synplify Pro FPGA synthesis software. Verilog, VHDL and SystemVerilog designers can now automatically generate an exhaustive set of constraints that address false and multi-cycle paths that work with Synopsys’ Synplify Pro synthesis flow.
Blue Pearl’s software suite also accelerates embedded system development and improves design quality by their collaboration with ARM and IP providers.
So, once again, if you are planning on attending the 49the DAC in San Francisco, bounce over to Booth #714 to see the guys and gals from Blue Pearl demonstrate how their new Blue Pearl Software Suite addresses the needs of FPGA and ASIC designers for improving productivity and design quality. (If you see Shakeel, say “Max says Hi!”
to schedule a meeting and demo, For more information, please visit Blue Pearl Software at www.bluepearlsoftware.com
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