LONDON – EDA company Mentor Graphics Corp. and chip firm STMicroelectronics NV are joining with French government agencies and a number of companies with operations in the Grenoble region of France to form a nanoelectronics program within the Grenoble Institute of Technological Research (IRT).
The NanoElec R&D will focus on 3-D IC integration and integrated silicon-photonics. It is supported by the CEA-Leti research institute in partnership with ST, Mentor Graphics, Soitec, Schneider, ST-Ericsson, Bouygues, Presto Engineering and the Grenoble INP Institute of Technology teaching and research school, the Grenoble Ecole de Management school, the Joseph Fourier university, the INRIA (National Institute for Research in Computer Science and Control), the CNRS (National Center for Scientific Research), the Laue Langevin Institute, and the ESRF (European Synchrotron Radiation Facility).
CEA-Leti, which announced the program, did not give an indication of how much money would be spent on the program, when work would start or when results could be expected.
The development of 3-D IC packaging is in need of support in design, modeling, simulation, manufacturing and testing. The main objective of the IRT's 3-D IC program is to validate an overall approach to 3D IC integration through a dedicated technological platform, taking into account the design, technological processes and characterization aspects. The integrated silicon photonics research will focus on chip-to-chip links and intra-chip communications where silicon integration should lead to lower costs and smaller systems.
"As with 3-D IC integration, silicon photonics has been the subject of joint work between the CEA and ST for several years. Thanks to the NanoElec IRT, the key players and all the design and technology means can work together to accelerate developments and open the applications field," said Philippe Magarshack, corporate vice president at ST, in a statement issued by CEA-Leti.Related links and articles:
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