Cadence tools tape out 20-nm SoC test chip for ST

MANHASSET, NY -- Cadence Design Systems has announced it has helped tape out STMicroelectronics’ 20nm test SoC chip, an industry milestone for Cadence delivering an end-to-end mixed-signal design flow for 20 nm.
 
"Working together over the past two years, Cadence and STMicroelectronics successfully deployed an efficient methodology and design automation to address the requirements for designing complex mixed-signal SoCs," said Chi-Ping Hsu, senior vice president, research and development, Silicon Realization Group at Cadence, in a statement.

ST performed automated layout generation using Cadence Virtuoso Layout Suite into STMicroelectronics' custom IP design development, including foundation IP, PLL and video DAC. Designers used a 20nm design kit that enables advanced capability such as Modgens, constraints and space-based routing. The Encounter Digital Implementation (EDI) System provided 20nm physical implementation capabilities for the tapeout, handling 20nm process requirements during placement and optimization as well as routing.

"We selected Cadence at the start of our 20-nanometer development, and today's milestone demonstrates the success of that collaboration," said Philippe Magarshack, group vice president of Technology Research and Development at STMicroelectronics.

Cadence will be at the Design Automation Conference next week presenting technical papers as well as at the annual Management Day activities. Pankaj Mayor, a Cadence vice president, will be one of eight speakers and will present and take part on a panel session the afternoon session on "Tradeoffs and Choices for Emerging SoCs."

The other speakers at the Tuesday June 5 Management Day include Vincent Ratford, former senior vice president of Xilinx and now an independent consultant; Chi-Feng Wu VP Engineering, Realtek Semiconductor; Norbert Diesing, Director ofEngineering, PMC-Sierra; Ajoy Bose; President and CEO, Atrenta; Indavong Vongsavady, Director of Engineering, STMicroelectronics; Jitendra Khare , Directorof  Engineering, AppliedMicro; and  William Eklow, Distinguished Engineer, Cisco Systems.

Cadence will have also a prominent booth presence at DAC.

The Design Automation Conference runs from June 3 to 7 in San Francisco.