News & Analysis
IMEC looks at variability beyond 10 nm
Anne-Francoise Pele
6/1/2012 5:10 PM EDT
PARIS – CMOS technology scaling will go on for the foreseeable future but, as we enter the 10nm node, process complexity reduction and variability control will become crucial and drive technology decisions, said An Steegen, senior vice president process technology at Imec, at the annual IMEC Technology Forum last week at the Square meeting center in Brussels, Belgium.
Tomorrow’s smart systems will require more computing power and storage capacity, exceeding what today’s processors and memories can deliver. This drives the need for technology scaling.
In her keynote, Steegen explained how Imec is helping to enable chip scaling beyond 10 nm. Moore’s Law through 19 nm can be lithography-enabled but, after that, it is necessary to look at materials and new design architectures.
Steegen’s message was that CMOS scaling is still possible. It’s just harder. Driving to sub-15nm dimensions requires EUV lithography and advanced patterning. It also implies a migration towards 3D device architectures such as FinFET and calls for material innovation with high-mobility channel materials.
Moore’s law continues but, Steegen specified, it increases complexity, cost and variability. New technology and design solutions together with co-optimization are required.
“The good news is that CMOS still scales, from planar Si device architectures (20 nm) to FinFET device architectures (14 nm) to better control short channel effects. But when you scale, when you introduce new materials, variability increases,” she stated.
Source: Imec
In a post-conference discussion with EE Times, Steegen provided more details on the variability issue as we move beyond 10 nm.
“Moving to fully-depleted channel devices like FinFET, allowing us to minimize doping in the channel, we have alleviated some of the variability issues associated with random dopants,” Steegen explained. “This is reflected in the reduced device mismatch. However, with non-planar devices, new variability emerges. With sidewall conduction and increase surface-to-volume ratio, trap and defect induced variation (eg. Low-Freq Noise, BTI reliability, etc.) become more important.
She continued: “Some of these new factors carry into 10nm technology. Beyond this, we expect new variability influences due to new material in the channel and advanced gate-stack modules introduced to boost device performance. New random defects may arise from the challenging integration (eg. Selective epitaxial growth of the heterostructure). Moreover, this material alters the interaction between the channel carriers and the traps/defects giving rise to changes in reliability, and noise.”
When asked what needs to be done to ease the variability issue, Steegen explained that Imec is looking into engineering the material to improve on quality.
There is also fundamental study on how to engineer the energy bands of the channel material to optimize reliability and performance. For instance, she noted, “we have looked into the engineering of implant-free quantum well SiGe channel devices to improved NBTI reliability. Work is ongoing to study the approach for FinFET devices for beyond 14nm applications.”
Steegen explained that, as part of the program, Imec is working to identify paradigm shifts in design. The research institute explores potential solutions, some of which require support by EDA tools. For that purpose, Imec collaborates with EDA vendors in such diverse domains as 3D Design-For-Test, TCAD, impact of litho options on P&R, OPC, 3D system design exploration, etc.
Her last words at the conference were encouraging. “Variability and cost must be considered as from the beginning. We have been reinventing ourselves many many times in the semiconductor industry. We will do it again and again,” she concluded.
Read also:
ARM CTO looks at architecture scaling for 2020 solutions
Tomorrow’s smart systems will require more computing power and storage capacity, exceeding what today’s processors and memories can deliver. This drives the need for technology scaling.
In her keynote, Steegen explained how Imec is helping to enable chip scaling beyond 10 nm. Moore’s Law through 19 nm can be lithography-enabled but, after that, it is necessary to look at materials and new design architectures.
Steegen’s message was that CMOS scaling is still possible. It’s just harder. Driving to sub-15nm dimensions requires EUV lithography and advanced patterning. It also implies a migration towards 3D device architectures such as FinFET and calls for material innovation with high-mobility channel materials.
Moore’s law continues but, Steegen specified, it increases complexity, cost and variability. New technology and design solutions together with co-optimization are required.
“The good news is that CMOS still scales, from planar Si device architectures (20 nm) to FinFET device architectures (14 nm) to better control short channel effects. But when you scale, when you introduce new materials, variability increases,” she stated.
Source: Imec
In a post-conference discussion with EE Times, Steegen provided more details on the variability issue as we move beyond 10 nm.
“Moving to fully-depleted channel devices like FinFET, allowing us to minimize doping in the channel, we have alleviated some of the variability issues associated with random dopants,” Steegen explained. “This is reflected in the reduced device mismatch. However, with non-planar devices, new variability emerges. With sidewall conduction and increase surface-to-volume ratio, trap and defect induced variation (eg. Low-Freq Noise, BTI reliability, etc.) become more important.
She continued: “Some of these new factors carry into 10nm technology. Beyond this, we expect new variability influences due to new material in the channel and advanced gate-stack modules introduced to boost device performance. New random defects may arise from the challenging integration (eg. Selective epitaxial growth of the heterostructure). Moreover, this material alters the interaction between the channel carriers and the traps/defects giving rise to changes in reliability, and noise.”
When asked what needs to be done to ease the variability issue, Steegen explained that Imec is looking into engineering the material to improve on quality.
There is also fundamental study on how to engineer the energy bands of the channel material to optimize reliability and performance. For instance, she noted, “we have looked into the engineering of implant-free quantum well SiGe channel devices to improved NBTI reliability. Work is ongoing to study the approach for FinFET devices for beyond 14nm applications.”
Steegen explained that, as part of the program, Imec is working to identify paradigm shifts in design. The research institute explores potential solutions, some of which require support by EDA tools. For that purpose, Imec collaborates with EDA vendors in such diverse domains as 3D Design-For-Test, TCAD, impact of litho options on P&R, OPC, 3D system design exploration, etc.
Her last words at the conference were encouraging. “Variability and cost must be considered as from the beginning. We have been reinventing ourselves many many times in the semiconductor industry. We will do it again and again,” she concluded.
Read also:
ARM CTO looks at architecture scaling for 2020 solutions
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resistion
6/1/2012 9:41 PM EDT
The move to sidewall gate oxide actually presented an extra scaling impediment.
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goafrit
6/3/2012 7:10 AM EDT
I am concerned that companies are seeing this process migration as a strong competitive weapon. I do not think it makes a lot of difference if you are not Intel making these billion transistor microprocessors.
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yalanand
6/3/2012 9:02 AM EDT
Thanks for sharing the Variability challenges slide. This beautifully explains the challenges we face at different nodes. No doubt sub 10nm node we will face lot of issues but am sure with the latest technology available we will eventually break the 10nm node barrier.
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Yog-Sothoth
6/3/2012 1:07 PM EDT
These people who say 'Moores law will continue' probably never studied physics, perhaps even basic maths.
Silicon has a lattice constant of 5.43095 anstroms. 1 angstrom = 0.1nm i.e. the spacing between crystalline silicon atoms is about 0.5nm.
So once you get below 10nm, there aren't that many atoms in your channel. At 7nm you've got roughly 14.
Now, do you think you can make devices that operate in bulk mode when you're down to atomic scale (assuming you can pattern stuff similarly small)?
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Chipguy1
6/5/2012 4:09 PM EDT
Correct.
You may even be able to make the transistor smaller (.i.e. "7nm roughly 14 atoms") but the smaller transistor tends not to be better or even if the mean values of the transistor is "better" (improved performance or power) a product made with a billions of the transistors will not improve or will improve less due to variability ( i.e. some transistors have 13 atoms or the worse billion transistor might only have 5 atoms).
I think we are seeing the early signs of Moore's Law slowing already and your logic correct. For the most advanced node intels 22nm (where parts of the silicon fin are only ~7nm thick), , I do think at the transistor level a single CMOS inverter (2 transistor )improves power ~50% per intel's data ....but ivy bridge product shows much less if any power improvement. For example, Ivy bridge shows worse power. Actual number depends where you benchmark the part. One benchmark case is over clocking where the worse power leads to higher chip temperature.
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