GloFo, TSMC report process tech progress
6/5/2012 1:01 AM EDT
TSMC steps ahead in 28, 20, 3-D
Like TSMC, Globalfoundries will offer only one flavor of its 20 nm process, focusing on close work with engineers on design rules. “At 20nm collaboration is a must,” he said.
For its part, Cadence Design Systems, Inc. said TSMC qualified the Cadence Physical Verification Systems (PVS) for 28 nm design signoff. It also completed Phase I certification for TSMC's 20 nm process.
Chip designers can access online PVS files from TSMC for both processes, Cadence said. The tools support features to handle common issues around the use of double patterning for 20 nm designs such as improved color loop detection accuracy.
In addition, Cadence announced it has developed a design flow for Samsung's 20 nm foundry process which is now available for use in making test chips.
In a separate talk, an IBM engineer reported progress on design methods for double patterning at 20 nm and unfinished work for triple patterning required at 14 nm. Designers need to clearly separate the portions of designs on first and second masks, watch for overlaps and use stitching to repair some double-patterning errors.
“This is no longer a Powerpoint fantasy, but has been integrated into fully functioning flows,” said Lars Liebman of IBM in a tutorial. “All the big EDA companies now have solutions to the coloring problem [in double patterning], but there are challenges in three-color mapping for 14 nm and no guaranteed solutions yet,” he said.
Separately, Globalfoundries and TSMC reported progress developing partnerships and processes for 3-D chip stacks.
Globalfoundries said it is working in parallel on 2.5 and 3-D ICs, also at Fab 8. It has partnerships with packaging companies Amkor Technology, ASE Group and StatsChipPAC at different levels on the various approaches. So far the companies have seen rising interest in the 2.5-D designs using silicon interposers, Chian said.
In a DAC tutorial, TSMC detailed its work on 3-D ICs with through silicon vias supporting Wide I/O controllers and memories. Specifically, it described a test chip including a 28 nm mobile applications processor, a 45
nm memory die and a 65 nm wireless I/O chip in a single package.
TSMC said it has taped out the test chip using a so-called Chip-on-Wafer-on-Substrate process with help from Cadence. The companies have yet to resolve some issues in thermal dissipation and package-level testing.
Nevertheless, “there are no major showstoppers,” said Frank Lee of TSMC in the tutorial. “Starting this year, you will see prototypes,” he said.