TI details TSV integration in 28-nm CMOS
6/13/2012 7:31 PM EDT
SAN FRANCISCO—Texas Instruments Inc. Wednesday (June 13) detailed progress in integrating through-silicon-vias (TSVs) into the company's advanced 28-nm CMOS process with little or no impact on nearby transistors.
In a paper due to be presented at the 2012 Symposia on VLSI Technology and Circuits in Honolulu, Hawaii, TI researchers were set to show results indicating minimal effect on transistors within 4 microns of TSV placement. The paper that researchers were to present also describes the use of nanobeam diffraction to measure near-TSV silicon strain on fully processed wafers to study the net effect of stressors.
"We can successfully integrate TSVs into 28-nm CMOS and have little or no effect on the transistors," said Jeff Brighton, director of CMOS 3-D IC technology development, at TI. "That's a critical stepping stone on the path to 3-D integration."
Three-dimensional chips using TSVs—which connect levels of die to each other—have been in development for years. Intel Corp. is currently in production of its 22-nm 3-D chips, which use a technology that the company refers to as tri-gate transistors.
Brighton, who is also a TI Fellow, said he is not aware of any paper publication prior to TI's Wednesday describing implementation of TSVs at advanced technology nodes. "I am sure there are others who could probably claim similar accomplishments, but we are claiming them," Brighton said.
TI has yet to announce when it plans to put into production chips using TSVs. Brighton declined to comment on a target date, but said the company was integrating TSVs into its 28-nm CMOS process and would be ready to implement them.
"There's always more work to be done," Brighton added. "I think we are fairly satisfied with the progress to date. I feel that most of the systematic issues in the wafer processing and packaging side are mostly behind us. Btu there are still yield improvements to be done, and always will be."
The paper, "Practical Implications of Via-Middle Cu TSV-induced Stress in a 28nm CMOS Technology for Wide-IO Logic-Memory Interconnect," was authored by TI researchers Jeff West, Youn Sung Choi and Catherine Vartuli.