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Adele.Hars
@michigan. the Leti figure you're citing for FD-SOI Si thickness is ...
michigan
A little confusion here: W Lg implys that W is less than Lg.
Ecosystem emerges around new mobile chip tech
George Leopold
7/11/2012 12:15 PM EDT
Manufacturing, supply chain are key
Leti has been working with IBM researchers in Albany, N.Y., and the French SOI wafer maker Soitec to develop FDSOI technology. The deal with ST-Ericsson gives the technology a platform for further scaling to 20 nm and lower, the Grenoble-based research institute said.
Leti researchers attribute performance gains to smaller gate lengths at 22 nm that reduce device parasitics. The resulting performance boost, along with the use of a technique called back-gate biasing to reduce power consumption, could provide device makers with “significant differentiation” in the mobile market, ST’s Magarshack contended.
He added that ST is now working with Globalfoundries to “enable the ecosystem for FDSOI.” Ron Moore of chip IP vendor ARM added that the next step will be extending the power-consumption benefits of the process technology to servers and the rest of the mobile infrastructure.
(Moore noted that the current infrastructure works out to roughly one server to deliver content to 600 smartphones. The number of servers needed to support the millions of new, full-feature smartphones expected to be sold around the world in the next few years would explode without significant reductions in power consumption and performance gains, Moore said.)
The partners acknowledged that their competition with Intel for the next generation of mobile chips comes down to demonstrating the ability to manufacture chips based on FDSOI technology while reducing risks in the mobile market for device makers. While Intel’s FinFET approach is not expected to enter production until the chip giant rolls out its 14-nm process technology, FDSOI proponents said they will be ready at 28 nm while continuing to scale to 20 nm.
“The supply chain will be there,” insisted Horacio Mendez, executive director of SOI Industry Consortium, adding that it will take six to nine months to ramp up to full production capacity. “The supply chain [for FDSOI) is not an issue we need to be worried about,” he claimed.
Beyond the ST-Ericsson joint venture, however, the SOI consortium has little to show so far in the way of customers among device makers. Mendez conceded that FDSOI performance and power “data is the only thing that convinces people.” He insisted that the group’s data will eventually show that it can help manage device makers’ risk in the hyper-competitive mobile market.
Leti has been working with IBM researchers in Albany, N.Y., and the French SOI wafer maker Soitec to develop FDSOI technology. The deal with ST-Ericsson gives the technology a platform for further scaling to 20 nm and lower, the Grenoble-based research institute said.
Leti researchers attribute performance gains to smaller gate lengths at 22 nm that reduce device parasitics. The resulting performance boost, along with the use of a technique called back-gate biasing to reduce power consumption, could provide device makers with “significant differentiation” in the mobile market, ST’s Magarshack contended.
He added that ST is now working with Globalfoundries to “enable the ecosystem for FDSOI.” Ron Moore of chip IP vendor ARM added that the next step will be extending the power-consumption benefits of the process technology to servers and the rest of the mobile infrastructure.
(Moore noted that the current infrastructure works out to roughly one server to deliver content to 600 smartphones. The number of servers needed to support the millions of new, full-feature smartphones expected to be sold around the world in the next few years would explode without significant reductions in power consumption and performance gains, Moore said.)
The partners acknowledged that their competition with Intel for the next generation of mobile chips comes down to demonstrating the ability to manufacture chips based on FDSOI technology while reducing risks in the mobile market for device makers. While Intel’s FinFET approach is not expected to enter production until the chip giant rolls out its 14-nm process technology, FDSOI proponents said they will be ready at 28 nm while continuing to scale to 20 nm.
“The supply chain will be there,” insisted Horacio Mendez, executive director of SOI Industry Consortium, adding that it will take six to nine months to ramp up to full production capacity. “The supply chain [for FDSOI) is not an issue we need to be worried about,” he claimed.
Beyond the ST-Ericsson joint venture, however, the SOI consortium has little to show so far in the way of customers among device makers. Mendez conceded that FDSOI performance and power “data is the only thing that convinces people.” He insisted that the group’s data will eventually show that it can help manage device makers’ risk in the hyper-competitive mobile market.
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Adele.Hars
7/11/2012 6:04 PM EDT
Indeed it was a great panel -- Chenming Hu of UC Berkeley and inventor of the FD-SOI technology was on it, too.
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Adele.Hars
7/12/2012 12:01 PM EDT
Since posting this comment, it's been pointed out to me that many people (JP Colinge, D.Flandre, researchers at Hitachi and many more...) did seminal work on fully-depleted/thin body transistors leveraging SOI. We think of this as new, but the industry's been quietly working on this for over 25 years!
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goafrit
7/11/2012 8:23 PM EDT
I hope this makes real progress. We need alternatives because if not contained, Intel will dominate the industry and set prices without fear of losing markets
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Hillol
7/11/2012 8:55 PM EDT
agree
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GroovyGeek
7/12/2012 2:59 AM EDT
And you think the IBM alliance is the answer? IBM lost relevance as a process technology pace-setter at least a decade ago. Mobile chips tend to have slim margins, and the substrates required for FD-SOI are expensive, adding the equivalent of at least one metal layer to the overall price of a chip. I can see why Soitec is pushing this, but I am not aware of a single demonstrated benefit of FD-SOI, and several well documented downsides (self-heating, floating body effects).
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SiliconAsia
7/12/2012 11:47 AM EDT
Agree, This article talks about FDSOI as if Intel never compared this to FinFet or any other process technology options. FDSOI or SOI in general was known to semiconductor for long and its benefits and downsides are well documented. In fact if you ruled out the price/cost factor of SOI, there are other technologies which can deliver much better performance/power than SOI.
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the_floating_ gate
7/12/2012 1:12 PM EDT
Of course Intel looked at SOI...and Bohr even agrees that some will use SOI but based on Intel's evaluation they rejected it.
4/16/2012 7:29 PM EDT
Mark Bohr addresses SOI versus bulk
One on One with M. Bohr
http://semimd.com/blog/2011/07/14/one-on-one-with-mark-bohr/
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the_floating_ gate
7/12/2012 1:20 PM EDT
"IBM lost relevance as a process technology pace-setter at least a decade ago."
10 years ago IBM screwed up big time pushing SOG (SiLK)in conjunction with copper interconnect.
UMC licensed the technology from IBM but dropped it because they figured out SiLK was not working.
And now gate first debacle - it's good for one node...
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Stanley_
7/13/2012 10:15 AM EDT
"While Intel’s FinFET approach is not expected to enter production until the chip giant rolls out its 14-nm process technology" Isn't it true that Ivy Bridge is using 22nm Tri-Gate, and already in market?
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chanj
7/14/2012 6:05 PM EDT
A consortium for better mobile processor makes total sense. One of the many keys solution of reducing power consumption is by achieving complete integration. There may be more than 1 consortia formed due to competitive and political reasons. If it is acceptable to the industry, 1 is always better than multiple. Nonetheless, the industry and market will drive the direction.
An interesting comment from Moore,
"the current infrastructure works out to roughly one server to deliver content to 600 smartphones"
I believe it depends on the kind of server and memory capacity. In addition, the type of services will affect the number of smartphones, or in general, mobile devices a server can deal with. To my experience, a dual Xeon with 128GB of memory shall be able to deal with thousands of simultaneous connections. If Moore is talking about ARM based servers, I have no doubt improvement is necessary.
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michigan
8/31/2012 1:34 PM EDT
It sound like a battle between planer FD SOI by new IBM alliances versus FD Trigate FinFETs by Intel has been declared. The key word here is FD (fully depleted) because both 22-nm transistor for IBM and Intel must be fully depleted to suppress the leakage current or short channel effects. Recently, Leti at the 2011 SOI conference has showed that ultra-thin/un-doped 6nm Si film is required for 22/20nm FDSOI to suppress the leakage current. For the 14nm FDSOI an extremely thin 4nm or less Si film may be required. However, Soitec can’t deliver such an ultrathin 6/4nm film in manufacturing. What Soitec can deliver is 12nm Si film and 25nm BOX for 22/20nm nodes. IBM and its alliance members also published FD SOI with 6.5/7 nm Si films at 2012 VLSI Symposium, but these are test chip data, not manufacture-able by Soitec.
Meanwhile, for FD finFETs the fin width (W) less than Lg (gate length) or W Lg is only required to suppress the leakage current. It means for 22nm node the fin W can have 21nm or less versus 6nm for FDSOI, and for 14nm node the fin W of 13nm or less versus 4nm for FDSOI. This is enormous advantage for manufacturability of 22/14nm FD finFETs compared with FD SOI. Furthermore, the trigate fins can be doped to adjust Vt, and manufacturability of the tri-gate fins dictates the device scaling. That is why Intel FD FinFETs is in high Volume manufacturing for several months, but FD SOI is not and will not be. The battle is over! S kim
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michigan
8/31/2012 1:45 PM EDT
A little confusion here: W Lg implys that W is less than Lg.
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Adele.Hars
12/7/2012 3:44 AM EST
@michigan. the Leti figure you're citing for FD-SOI Si thickness is *post-processing". The current and next-gen wafers from Soitec et al meet all the requirements. This was explained very clearly by Bruce Doris of IBM a couple years ago, who said (and it is still true), "The top silicon of the starting wafer (currently 12nm) has to be thicker than the final target thickness of the channel since some Si is used up in the process flow prior to final channel thickness definition. " http://www.advancedsubstratenews.com/2010/07/etsoi-substrates-what-we-need/ A lot has happened since you posted this comment -- I think you may find that the battle has just begun...
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