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Adele.Hars
@michigan -- not sure why there's this misunderstanding -- all the current ...
michigan
Recently professor Asenov of GSS pointed out the disadvantages of the bulk based ...
UMC set to beat TSMC to FinFET process
Peter Clarke
7/27/2012 7:59 AM EDT
LONDON – Taiwan's United Microelectronics Corp. (UMC), which has been a struggling number two behind foundry leader Taiwan Semiconductor Manufacturing Co. Ltd. (TSMC), could get one over on its long-time rival by being first in production with FinFET process technology.
This is despite the fact that TSMC (Hsinchu, Taiwan) was one of the originators of the FinFET idea more than a decade ago.
UMC (Hsinchu, Taiwan), courtesy of a licensing deal with computing giant IBM, could be in production with a 20-nm FinFET process as soon as in the second-half of 2014; up to a year ahead of the latest disclosed timing from TSMC.
The process UMC has licensed is for FinFETs on bulk silicon rather than on silicon-on-insulator wafers, according to a spokesperson. This makes it easier to introduce quickly after a running a 20-nm bulk CMOS process. Reports suggest that making sure fins are well defined with a rectangular cross section can make a marked difference to performance and that making FinFETs on SOI wafers could produce a further improvement in leakage current performance.
Shih-Wei Sun, CEO of UMC did not demur when it was put to him that UMC was targeting 2014 for the introduction of 20-nm FinFETs, in a conference call to discuss UMC's second quarter financial results.
He added that UMC's first FinFET would be based on the same 20-nm back-end process as a 20-nm planar CMOS. He said most companies were doing this but that some were defining it as a 16- or 14-nm process. He added that this was really a marketing definition. This is in line with an explanation of a two-step 20-nm process given to analysts recently by Eric Meurice, CEO of lithography equipment vendor ASML.
The latest from TSMC is that its first FinFET process will be at 16-nm and that it is due to ramp in the second half of 2015. Although if TSMC is also using its 20-nm back-end for its FinFET process it may have the option to bring forward its timetable for a FinFET process.
Related links and articles:
FinFETs-on-SOI can double battery life, says GSS
ARM, TSMC sign deal to ease FinFET process introduction
ASML outlines a FinFET process 'two-step'
UMC licenses IBM technology for 20-nm FinFETs
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rick.merritt
7/27/2012 11:40 PM EDT
Go UMC!
I was impressed with management when I visited earlier this year. They are smart, open and engaged.
But given history, a process deal with IBM is no slam dunk. Silk anyone?
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HS_SemiPro
7/28/2012 12:34 AM EDT
Tech cannot be fully developed yet, as IBM or its JDA partners aren't introducing it at 20nm. So more development would definitely be needed. However IBM JDA partners have been co-developing tech for many generations including ST, GF, & Samsung, so I am not too worried for IBM technology
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chipmonk
7/30/2012 6:47 PM EDT
not to mention IBM's pushing HKMG first -a one node wonder that blew up when scaled down to 28 nm
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resistion
7/29/2012 5:04 PM EDT
I don't see why TSMC can't offer a FinFET option at 20 nm.
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FoundryMKT
7/29/2012 8:13 PM EDT
No, I don't think so. You need more study on the progress of IBM's FinFET technologies.
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resistion
7/29/2012 8:34 PM EDT
There is one report of TSMC preparing 20 nm FinFET for ARM.
http://www.electronicsweekly.com/blogs/david-manners-semiconductor-blog/2012/07/arm-tsmc-leading-intel-in-soc.html
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peter.clarke
7/30/2012 10:08 AM EDT
TSMC refers to their first FinFET process as 16-nm.......but ASML and UMC have both said that regardless of that these initial foundry FinFET processes are called they will be the application of FinFET front-end processing to the same back-end interconnect used at 20-nm
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Chipguy1
7/30/2012 10:23 PM EDT
Peter,
Yes. All data seems to suggest foundry 16nm node is finfet with 20nm design rules
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BJ-5
7/29/2012 10:37 PM EDT
Not a credible story.
TSMC has 2 year lead at 28mm
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resistion
7/31/2012 1:16 AM EDT
Lithographically, foundry's 28 nm should be close to Intel's 22 nm at about 45 nm half-pitch.
But the fin process adds extra cost without helping transistor density. I'd be curious if foundry 28 nm transistors perform so poorly against Intel's 22 nm FinFET.
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BJ-5
7/31/2012 10:30 AM EDT
Resistion,
Spot on. Intel's metal system is only on par with foundry 28nm and that largely set SOC die size. Bottom line intel 22nm will not be cost competitive for mobile SOC. This along with intel 22nm (at present time) not supporting adequate SOC device types and the technology having a lot of variation issues (from the sloped fins causing gate oxide and WF variation) is what the industry assessment is at this time.
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michigan
8/4/2012 2:45 PM EDT
Recently professor Asenov of GSS pointed out the disadvantages of the bulk based Intel’s 22-nm FinFET and superiorities of FinFETS on SOI, citing 50% less leakage current, smaller variability, and not extendable to 14-nm without SIO substrate….etc. However, the FINFETon SOI may be not even manufacturable as I commented in “FinFETs-on-SOI can double battery Life, says GSS”, 7/27/2012, EE Times News. The two problems intrinsic to FinFETs on SOI are floating body effect and self-heating that need to be overcomed. UMC licensed IBM technology for 20-nm FinFETs, but the process UMC has licensed is for FinFETs on bulk silicon rather than on SOI wafers. This is rather surprising since IBM has always promoted FinFETs on SOI. TSMC has been developing bulk 20-nm FinFETs for several years, and published its transistor transfer characteristics at 2010 IEDM. I doubt that UMC can beat TSMC on bulk based FinFET technology development race. Tsmc is at least three years ahead of UMC in 20-nm bulk technology. S. kim
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Adele.Hars
8/7/2012 6:17 PM EDT
@michigan -- not sure why there's this misunderstanding -- all the current literature that I've seen indicates that there is *no* floating body (FB) / history etc. effects in FinFETs on SOI. FinFETs -- whether on bulk or SOI -- are a fully depleted technology. FB/history effect is strictly a PD (partially depleted)-SOI phenomenon. IBM, btw, is sticking with PD-SOI for their high-perf big iron until they make the switch to FinFETs on SOI at 14nm. The SOI Consortium contends that in fact FinFETs on SOI are easier to manufacture -- cutting up to a year off the mfg learning curve, and that that plus fewer process steps ultimately makes the SOI version cheaper. SHE (self-heating effect) is a challenge for FinFETs in both SOI and bulk. FinFETs are part of the MuGFET family of vertical structures, which has been studied since Hitachi first proposed them (on SOI!) in 1989. As such, the industry's been working on vertical structures like FinFETs for over two decades. The research and development has very deep roots....
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