Intel's Bohr sees path to 10-nm chips

9/13/2012 7:51 AM EDT

Aren't the 22 nm fins double-patterned already?

Previously didn't they say 10 nm was quintuple-patterned?

9/13/2012 12:08 PM EDT

In his talk, Bohr said many features in the 22nm process use 80 pitch features, a size chose for this generation because they can be single patterned.

He did not say anything about double patterning at 22nm or quintuple patterning on any process.

9/13/2012 10:37 PM EDT

10nm...looks like we are on the verge of things getting very interesting.

9/14/2012 3:35 AM EDT

A good research and with targets like reducing cost per transistor every year.

9/14/2012 9:09 AM EDT

I have no doubt that Intel can get to 10 nm with quadruple patterning, but will they be able to suppport a reasonable business model once they get there? And what happens after 10 nm? Is that the end of scaling unless and until EUV litho kicks in at reasonable cost?

9/14/2012 12:04 PM EDT

This is important work. If Moore's law ends and software's corrolary to Moore's law (code size doubling every two years) keeps trucking, we're doomed.

9/14/2012 8:17 PM EDT

Slowed scaling just means that more emphasis has to be put on other aspects of the design. We won't be able to rely on just buying the latest and greatest piece of silicon. Personally I think this is going to be great motivation for better understanding of hardware and the implications of poor coding/software design.

9/17/2012 1:24 PM EDT

One way forward is for only the parts of the chip that need the smaller geometries be built with the slower litho processes. I have not seen any discussion of this. it is always xxnm

9/17/2012 1:25 PM EDT

When Morres law becomes lesse's law?

9/20/2012 9:36 PM EDT

In theory Intel’s Trigate FinFETs can extend to 10nm beyond as long as lithography can permit because for FinFETs to be fully depleted to suppress the leakage current or short channel effects the fin width (W) less than gate length (Lg) is only required. For 10nm node and below, however, new physical phenomena not seen in wide fin W will occur. The fin W at bottom of the fin for 10nm node and below may approach 6nm or less and 5nm at top of the fin. However, for the fin W with such an extremely thin 6nm may hit the CMOS scaling wall or the end of the Moore’s Law because of the quantum mechanical effects imposed by the structural quantum confinement. It means in simple terms that the electrons within such extremely thin 6nm fin W do not behave like classical particles any more, but instead act as waves. As a result, drift and diffusion based classical semiconductor physics is no longer applicable. Instead, the electron behavior is now described by the quantum mechanical physics based Schrodinger’s wave equations and is subjected to Heisenberg’s uncertainty principle.
The impact of such quantum confinement on the electrical characteristics is a significant increase in threshold voltage Vt due to the mobility degradation caused by decrease in the inversion layer thickness. The Vt increase depends on how thin the fin W is. But this adds to the variation in Vt due to the short channel effect with varying Lg. The other more critical effect is very large variations or uncertainties in transistor transfer characteristics such as Vt, Id/Vg, ID/Vd, DIBL, SS (sub-threshold slop), and SRAM noise. These are physical limits derived from quantum mechanical effects, limiting to the channel length to 10nm node with fin W of 6nm. Process variations not considered here could further adversely impact the variability of finFETs electrical characteristics. Therefore, in my opinion the 10 nm node with fin W 6nm or less will not be manufacturable or the end of CMOS scaling. S Kim