Intel, rivals gird for IC manufacturing showdown

9/24/2012 3:59 PM EDT

My foundry contact has studied Intel's 22nm SOC FinFET manufacturing flow and claims that it is not cost effective (compared to foundry 28nm/32nm) to manufacture mobile chips hence even Intel over next 3 years will still make most of its Infineon mobile cell phone chipsets at TSMC.

Chips such as the 2 main chips in Apple's iphone 5: MDM9615 and A6 have an average ASP of $20 compared to similar die size X86 that Intel sells for $100-200)

9/24/2012 7:13 PM EDT

Peter,

I have seen others post this as well. Can you address why repeating the intel spin on "manufacturing show down" makes any sense when today most advanced atom SOC is on 32nm and will stay that way until end of 2013 ! while Qualcomm is shipping 50M units 28nm this year in just the iPhone 5 design alone and

(2) I thought all you guys were writing about intel winning mobile market with 22nm finfet last year (2011) and intel has not demo anything close to A6 CPU or graphic power/performance (at mobIle power level) .... Even demoed something close to what is already shipping !

9/25/2012 6:00 AM EDT

@James

I was not aware that Intel has a position on a "manufacturing show down" and therefore did not try to repeat it.

My intention was to tell readers that papers will be presented at IEDM on many of the leading-edge process technologies that will be producing chips in the near future. And therefore San Francisco in early December would be a good place to find out more.

The rigor of the IEDM review process means that these should be detailed, quantitative presentations albeit likely to be only on certain aspects of each of these processes.

From my perusal of the program the 14-nm logic node is being discussed mainly by academic groups looking at aspects of doping and strain in individual transistors.

To your second point. All what guys?

9/25/2012 11:55 AM EDT

22nm not cost-effective ? I suppose that depends upon the level of integration. While it's probably not a cost-savings to replace small individual 32nm devices with 22nm, there is a definite cost-savings thru higher integration at smaller process geometries to reduce PCB area, total BOM, and possibly power-savings as well.

9/25/2012 12:34 PM EDT

Intel cannot afford to implement beyond 20nm. SandyBridge Moble Mfg Cost $0.40 per sq mil dice area.

US Government & Intel are concealing Corp. is looted by employees and stakeholders & Bankrupt in future terms.

5 Sources; 1) infiltration by cartel organized network crime; 2) banked cost constructing surplus barrier limiting competitors beyond 32 nm; 3rd, theft from stockholder’s administers cost of channel price fix tie; 4th, theft fm end customers charged price fix in invoice plus monopoly overcharges. Likely PC end buyers will see some recovery. 5th industrial theft processors dumped at price less than cost. 5 categories record $178,713,547,976 misrepresented & unreported cost burden on Intel.

Where are present cost burdens? 1st, inventories Xeon Westmere EX, Aarondale, Sandy Bridge Desktop & Mobile. 3 Issues; first, surplus processors banked in channels on deferred revenue recognition; 2nd, completed systems stalled in channels showing now what is occurring inside Intel; 3rd, surplus banked goods; processors, systems, repurposed for apps that will compete against Intel future product placing burden on industry in total.

Finally, one must ask why Intel is sustaining price on prior runs instead of flushing at cost to recover investment burden?

For Intel to dump inventories means twin tower effect on supply chain. Processor margins eliminated AMD becomes system house to capture remaining downstream producer values. Same for other processor design producers impacted by surplus raining down.

Collapse flattens Intel’s long time channel & contract manufacturers finally take over for certain.

Final question was price hold a hidden condition in Docket 9341 consent agreement? It’s time for regulatory mechanisms in this country that are supposed to police monopolization, cartel and investment fraud, including at Intel, to do that job of be replaced with administrations that will do that job.

Respectfully submitted,
Mike Bruzzone

9/25/2012 2:03 PM EDT

Will there be any discussion of planned process metrology?

9/25/2012 10:40 PM EDT

@bruzzer is this some innovative marketing statement? Who is the client.

9/26/2012 6:52 AM EDT

Mike Bruzzone Should be mentally ill

9/26/2012 10:00 AM EDT

PHW_#1,

Confirmed--Intel baseband will use foundry (mostly TSMC) for next 2-3 years since Intel's internal cost is too high. This is because Intel's 22nm to get to yield has more restrictive design rules (increases die size). Restrictive design rules are on logic, analog, I/O, and back-end metal. Intel will never have competitive baseband chips in its 22nm SOC.

Same is true for Intel's atom line, 22nm SOC Intel chip name Valleyview)...it is that part again due to the restrictive design rules that will not be competitive on cost.

9/27/2012 12:50 AM EDT

Mike Bruzzone is fm IBM PC Board add on’s; Turbo, Memory, Network Card, 1st 2.5 D PC AT graphics card, 33 PC introductions including fastest 386 33 class workstation on memory write back; co host 1990 SIGGRAPH, first PC Standard MP C&T Corallary Chip set, first not Intel 387 math coprocessor, first not Intel 486SLC/486DLC, 486S Intel substitute microprocessors, first Nx586 replacement platform, first 16 bit bus 32 bit core Mini RISC, first 32 bit performance Mini RISC SOC, first I frame editor, first fast486120, some Alpha&NT, first low power C6 desktop & first less than $1,000 PC. Current research tracks include economics of fabrication; member Silicon Valley Round Table, intersection x86 & ARM, HPC/GPU/APU, resistive RAMs & advanced non volatile memory structures.

Mike Bruzzone is an Intel competitive strategist specializing in not Intel product commercialization who is invited discovery technical assistant by Federal Trade Commission Bureau of Competition for FTC v Intel Docket 9288, lettered to work report Assistant AG Antitrust Division of the State of California Department of Justice for defining Sherman Act Section One violation, a EUCC domestic U.S point of contact Monti/Kroes/Martinez Commissions, SEC recognized Relator by letter, Federal False Claims Act Original Source by letter U.S. Attorney Northern California District, recognized Relator Intel monopoly procurement theft in fifty States, four territories and the District of Columbia, invited discovery technical assistant FTC Chairman Referral back into Bureau of Competition Docket 9341, FBI original source of Intel Dealing Cartel 1996.

Criminal sub groups operating in Intel have in past positioned detractors as mentally ill, including their own employees up high in the enterprise who question Intel’s invented reality in pursuit of error correction, remedies, maintenance of democratic capitalism & industrial social responsibilities. For consultancy inquire campmkting@aol.com

9/28/2012 10:49 AM EDT

So why not mix and match these techniques using the best for the type of circuits.
Finfets for fast transievers with power gating when not in use. Others that do not need the speed or low power switching can be other types.
I was drawing finfets in my notebook in the early 90's sitting in ee classes.

10/4/2012 11:46 AM EDT

I am little confused by the title “Intel, Rivals gird for IC manufacturing showdown” because IEDM (International Electron Device Meeting) has not been a forum for IC manufacturing showdown, instead mainly for new research devices, new transistor analysis techniques, device physics, scaling limits…etc. Furthermore, among the three major technologies for 22/20 nodes, FDFinFETs by Intel, FDSOI/UTTBB by IBM Alliances and planar bulk Si by Samsung to be presented here at IEDM, Intel is the only one manufacturing its FDFinFETs for several months now. IBM and Samsung have not announced yet when their technologies will be manufacturing. Therefore, in my opinion the word manufacturability would be more appropriate than “manufacturing” because manufactrability will become the determining factor for ultimate CMOS scaling for 22/20nm nodes and beyond. In order to have manufacturability assessments the transistor electrical characteristics such as VT, dId/dVg, dId/dVd, DIBL, and SS (sub-threshold slope) should be measured, and used also as minimum criteria for paper selection. I have been attending IEDM for over ten years. The paper selection has significantly deteriorated recently as indicated by a significant number of the papers presented don’t meet the minimum criteria. Skim