Road to ARM TechCon: Cortex-M0+ hits spot for low-power systems

System level features
The Cortex-M0+ processor supports a new I/O interface which allows single cycle accesses and so enables faster I/O port operations. The processor’s I/O interface is a generic 32-bit interface to which microcontroller vendors then add their own I/O port peripherals. With this I/O interface, the Cortex-M0+ processor can perform peripheral accesses faster than any of the popular microcontrollers.

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Since the I/O interface is part of the system’s memory map, the I/O register on this interface can be accessed with normal pointers in C and does not require specific C language extension features such as special data types.

Because accesses to the AMBA® AHB-Lite™ and the single cycle I/O interface can be made concurrently, the Cortex-M0+ processor can fetch the next instructions while accessing the I/Os. This enables single cycle I/O accesses to be sustained for as long as needed.

Power-sensitive applications will also benefit from this improvement, by either running at lower speed for the same I/O toggling frequency, or by completing the I/O control more quickly, then going faster into a sleep mode.



The Cortex-M0+ processor also includes many useful features from the Cortex-M3 and Cortex-M4 processors previously not available in the Cortex-M0 processor. For example, it supports privileged and unprivileged execution levels, and a Memory Protection Unit (MPU), which is similar to that in the Cortex- M3 and Cortex-M4 processors. The MPU is a programmable component with 8 programmable regions, and can be used by an OS to create access permission rules for various application tasks dynamically during run time. By using this mechanism, the design can prevent an application task from corrupting memory space used by other tasks and the OS kernel.