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marcos83
iniewski
10nm in 2 years??? That would beat Moore's law expectations...and we are ...
Quad patterning a possibility at 10nm, says TSMC
Rick Merritt
10/30/2012 3:31 PM EDT
SANTA CLARA, Calif. – Quad patterning may be needed for 10-nm process technology if extreme ultraviolet (EUV) lithography is not ready in 2015 or so when Taiwan Semiconductor Manufacturing Co. expects to start early production of the technology.
That’s the view expressed by Jack Sun, chief technologist at TSMC, in a brief interview after his keynote at the ARM TechCon here Tuesday (Oct. 30). Sun said quad patterning--four passes through a lithography stepper using four different masks--was one of several options TSMC is exploring as it works on path finding for the process.
Earlier, Intel said it has found a way to make 10-nm chips using quad patterning that is still cost effective. It aims to start production of chips in the process in as little as two years.
[ARM TechCon 2012, the largest ARM design ecosystem under one roof, is Oct. 30 - Nov. 1 in Santa Clara. Click here to learn more]
In his keynote here, Sun showed the same near-term roadmap for TSMC the company showed at its own event earlier this month. It includes starting limited test production of 20-nm planar chips by the end of the year and a 16-nm FinFET process starting test production late next year.
Sun said the new 20-nm process holds traditional advances of as much as 35 percent in performance and power capabilities. New transistor structures like FinFETs will provide an even greater boost, he said.
As for 10-nm, TSMC “is in serious path finding development of it,” he said. “In the next five years, we can see down to 5 nm easily, but of course there are some path finding challenges yet to come,” he added.
Sun also reported TSMC has successfully made prototypes of both FPGAs and graphics processors using its Chip on Wafer on Substrate (CoWoS) process. The technique, also known as 2.5-D packaging, links multiple die laid side-by-side on a common substrate.
He also noted SMC reported in June progress making through silicon vias as small as 50 microns, about half the size of previous interconnects.
TSMC and partners in total spent an estimated $11,9 billion on their chip design and manufacturing ecosystem, Sun said. “That’s bigger than any single company, and its open--it is one of the biggest innovation forces” in the industry, he said.
Related story:
That’s the view expressed by Jack Sun, chief technologist at TSMC, in a brief interview after his keynote at the ARM TechCon here Tuesday (Oct. 30). Sun said quad patterning--four passes through a lithography stepper using four different masks--was one of several options TSMC is exploring as it works on path finding for the process.
Earlier, Intel said it has found a way to make 10-nm chips using quad patterning that is still cost effective. It aims to start production of chips in the process in as little as two years.
[ARM TechCon 2012, the largest ARM design ecosystem under one roof, is Oct. 30 - Nov. 1 in Santa Clara. Click here to learn more]
In his keynote here, Sun showed the same near-term roadmap for TSMC the company showed at its own event earlier this month. It includes starting limited test production of 20-nm planar chips by the end of the year and a 16-nm FinFET process starting test production late next year.
Sun said the new 20-nm process holds traditional advances of as much as 35 percent in performance and power capabilities. New transistor structures like FinFETs will provide an even greater boost, he said.As for 10-nm, TSMC “is in serious path finding development of it,” he said. “In the next five years, we can see down to 5 nm easily, but of course there are some path finding challenges yet to come,” he added.
Sun also reported TSMC has successfully made prototypes of both FPGAs and graphics processors using its Chip on Wafer on Substrate (CoWoS) process. The technique, also known as 2.5-D packaging, links multiple die laid side-by-side on a common substrate.
He also noted SMC reported in June progress making through silicon vias as small as 50 microns, about half the size of previous interconnects.
TSMC and partners in total spent an estimated $11,9 billion on their chip design and manufacturing ecosystem, Sun said. “That’s bigger than any single company, and its open--it is one of the biggest innovation forces” in the industry, he said.
Related story:
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resistion
11/2/2012 5:21 AM EDT
According to German BMBF, 14 nm not even ready until 2015, let alone 10 nm.
http://www.electroiq.com/articles/sst/2012/08/euv-lithography-project-launches-for-better-resolution-at-14nm.html
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resistion
11/2/2012 7:38 AM EDT
So it's pretty clear the timing is pretty bad for EUV.
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iniewski
11/2/2012 6:00 PM EDT
10nm in 2 years??? That would beat Moore's law expectations...and we are supposed to be facing fundamental limits at that point!
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marcos83
11/6/2012 8:02 AM EST
10nm with luck, tricks, bells and whistles.
ASML have yet to show anything less than 30nm with a normal operating EUV machine.
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