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Cadence, IBM push SOI FinFET design to 14-nm
Peter Clarke
11/2/2012 2:01 AM EDT
SANTA CLARA, Calif. – EDA vendor Cadence Design Systems Inc. said Tuesday (Oct. 30) it designed an ARM processor test chip aimed at implementation in a 14-nm silicon-on-insulator FinFET manufacturing process from IBM.
The design--based on an ARM Cortex-M0 core--is part of a multi-year agreement between ARM, Cadence and IBM to develop system-on-chip ICs at 14-nm and beyond.
The chip was developed to check parameters and intellectual property for design at the 14-nm node. Besides the ARM core, the design includes SRAM and other circuit blocks. Measurements of the test-chip can provide characterization data necessary for the development of FinFET-based physical IP by ARM, Cadence said. The design includes support for double patterning of lithography.
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"The tapeout of this 14-nm test chip is the culmination of the significant progress we have made with FinFET on SOI utilizing it's built-in dielectric isolation," said Gary Patton, vice president of IBM Semiconductor Research and Development Center, in a statement issued by Cadence (San Jose, Calif.).
The chip was designed with Cadence's Encounter digital design tools using FinFET standard cell libraries designed with Cadence's Virtuoso tools.
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