Big.little test results show promise, ARM reports

SANTA CLARA, Calif. – ARM reported a test chip using its A15 and A7 cores saved 50 percent on power consumption without sacrificing performance.  It also revealed a road map for enabling software for the so-called big.little initiative which pairs a large and small core.

The technology looks promising enough that even some chip makers outside the ARM ecosystem—such as Intel—might consider adopting it, said one analyst. Samsung is expected to sample the first big.little SoC, perhaps before the end of the year. Several chip makers have similar SoCs in development, said ARM.

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“Big.little is moving from a promising technology to something we think will be ubiquitous in low power systems, and we are quite happy with the progress so far,” said Brian Jeff, a product manager for ARM in a presentation on the topic at the ARM Tech Con here.

“There’s a lot of tuning to be done, but its working quite well today, we are a bit ahead of where we expected to be last year,” he added.

Big.little is based on an analysis of today’s mobile workloads. It showed they are divided into many relatively low performance apps that can be handled on a low power core and a few high performance ones that sometimes need a brawnier core. Big.little uses software that automates the job of choosing which job to run on which core to get work done quickly but with minimal energy.

Software developers at ARM and Linaro are currently working on two big.little modes.

A CPU Migration mode moves jobs between clusters of cores, has working software available now that will be ready for production before June. A big.little MP approach can assign individual threads to the best core, promises better results but requires more tuning and is in an earlier stage of development,

Separately, Jeff said the A15 probably will deliver about twice the performance of today’s A9, and the A7 will about match the A9 in performance. ARM’s test chip (below) used two A15s and three A7s with a DMC-400 memory controller all on a cache coherent interconnect in a 40 nm process.

“The MP stuff that I thought was rocket science when they talked about it last year is coming along quite well--that’s kind of the Holy Grail here,” said Kevin Krewell, editor of the Microprocessor Report. “Intel has the capability to do something like this with Atom, Core and Xeon cores,” he said.

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